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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 90/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
5.5 OTHER FUNCTIONAL
DESCRIPTIONS
5.5.1 Entering and Exiting Hold
Acknowledge
The bus hold acknowledge state, Th, is entered in
response to the HOLD input being asserted. In the
bus hold acknowledge state, the Intel386 DX floats
all output or bidirectional signals, except for HLDA.
HLDA is asserted as long as the Intel386 DX re-
mains in the bus hold acknowledge state. In the bus
hold acknowledge state, all inputs except HOLD,
RESET, BUSY
Y
, ERROR
Y
, and PEREQ are ig-
nored (also up to one rising edge on NMI is remem-
bered for processing when HOLD is no longer as-
serted).
231630–29
NOTE:
For maximum design flexibility the Intel386 DX has no
internal pullup resistors on its outputs. Your design may
require an external pullup on ADS
Y
and other Intel386
DX outputs to keep them negated during float periods.
Figure 5-25. Requesting Hold from Idle Bus
Th may be entered from a bus idle state as in Figure
5-25 or after the acknowledgement of the current
physical bus cycle if the LOCK
Y
signal is not assert-
ed, as in Figures 5-26 and 5-27. If HOLD is asserted
during a locked bus cycle, the Intel386 DX may exe-
cute one unlocked bus cycle before acknowledging
HOLD. If asserting BS16
Y
requires a second 16-bit
bus cycle to complete a physical operand transfer, it
is performed before HOLD is acknowledged, al-
though the bus state diagrams in Figures 5-13 and
5-20 do not indicate that detail.
Th is exited in response to the HOLD input being
negated. The following state will be Ti as in Figure
5-25 if no bus request is pending. The following bus
state will be T1 if a bus request is internally pending,
as in Figures 5-26 and 5-27.
Th is also exited in response to RESET being assert-
ed.
If a rising edge occurs on the edge-triggered NMI
input while in Th, the event is remembered as a non-
maskable interrupt 2 and is serviced when Th is exit-
ed, unless of course, the Intel386 DX is reset before
Th is exited.
5.5.2 Reset During Hold Acknowledge
RESET being asserted takes priority over HOLD be-
ing asserted. Therefore, Th is exited in reponse to
the RESET input being asserted. If RESET is assert-
ed while HOLD remains asserted, the Intel386 DX
drives its pins to defined states during reset, as in
Table 5-3 Pin State During Reset
, and performs
internal reset activity as usual.
If HOLD remains asserted when RESET is negated,
the Intel386 DX enters the hold acknowledge state
before performing its first bus cycle, provided HOLD
is still asserted when the Intel386 DX would other-
wise perform its first bus cycle. If HOLD remains as-
serted when RESET is negated, the BUSY
Y
input is
still sampled as usual to determine whether a self
test is being requested, and ERROR
Y
is still sam-
pled as usual to determine whether a Intel387 DX
coprocessor vs. an 80287 (or none) is present.
5.5.3 Bus Activity During and
Following Reset
RESET is the highest priority input signal, capable of
interrupting any processor activity when it is assert-
ed. A bus cycle in progress can be aborted at any
stage, or idle states or bus hold acknowledge states
discontinued so that the reset state is established.
RESET should remain asserted for at least 15 CLK2
periods to ensure it is recognized throughout the In-
tel386 DX, and at least 80 CLK2 periods if Intel386
DX self-test is going to be requested at the falling
edge. RESET asserted pulses less than 15 CLK2
periods may not be recognized. RESET pulses less
than 80 CLK2 periods followed by a self-test may
90
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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