參數(shù)資料
型號： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁數(shù)： 109/139頁
文件大小： 1587K
代理商： INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
Table 6-1. Intel386
TM
DX Instruction Set Clock Count Summary
(Continued)
CLOCK COUNT
NOTES
Real
Address
Mode or
Virtual
8086
Mode
Real
Address
Mode or
Virtual
8086
Mode
INSTRUCTION
FORMAT
Protected
Virtual
Address
Mode
Protected
Virtual
Address
Mode
SMSW
e
Store Machine
Status Word
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1
mod 1 0 0
r/m
2/2
2/2
b, c
h, l
STR
e
Store Task Register
To Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
mod 0 0 1
r/m
N/A
2/2
a
h
VERR
e
Verify Read Accesss
Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
mod 1 0 0
r/m
N/A
10/11
a
g, h, j, p
VERW
e
Verify Write Accesss
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
mod 1 0 1
r/m
N/A
15/16
a
g, h, j, p
INSTRUCTION NOTES FOR TABLE 6-1
Notes a through c apply to Intel386 DX Real Address Mode only:
a. This is a Protected Mode instruction. Attempted execution in Real Mode will result in exception 6 (invalid opcode).
b. Exception 13 fault (general protection) will occur in Real Mode if an operand reference is made that partially or fully
extends beyond the maximum CS, DS, ES, FS or GS limit, FFFFH. Exception 12 fault (stack segment limit violation or not
present) will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum SS limit.
c. This instruction may be executed in Real Mode. In Real Mode, its purpose is primarily to initialize the CPU for Protected
Mode.
Notes d through g apply to Intel386 DX Real Address Mode and Intel386 DX Protected Virtual Address Mode:
d. The Intel386 DX uses an early-out multiply algorithm. The actual number of clocks depends on the position of the most
significant bit in the operand (multiplier).
Clock counts given are minimum to maximum. To calculate actual clocks use the following formula:
Actual Clock
e
if m
k l
0 then max (
[
log
2
l
m
l
]
, 3)
a
b clocks:
if m
e
0 then 3
a
b clocks
In this formula, m is the multiplier, and
b
e
9 for register to register,
b
e
12 for memory to register,
b
e
10 for register with immediate to register,
b
e
11 for memory with immediate to register.
e. An exception may occur, depending on the value of the operand.
f. LOCK
Y
is automatically asserted, regardless of the presence or absence of the LOCK
Y
prefix.
g. LOCK
Y
is asserted during descriptor table accesses.
Notes h through r apply to Intel386 DX Protected Virtual Address Mode only:
h. Exception 13 fault (general protection violation) will occur if the memory operand in CS, DS, ES, FS or GS cannot be used
due to either a segment limit violation or access rights violation. If a stack limit is violated, an exception 12 (stack segment
limit violation or not present) occurs.
i. For segment load operations, the CPL, RPL, and DPL must agree with the privilege rules to avoid an exception 13 fault
(general protection violation). The segment’s descriptor must indicate ‘‘present’’ or exception 11 (CS, DS, ES, FS, GS not
present). If the SS register is loaded and a stack segment not present is detected, an exception 12 (stack segment limit
violation or not present) occurs.
j. All segment descriptor accesses in the GDT or LDT made by this instruction will automatically assert LOCK
Y
to maintain
descriptor integrity in multiprocessor systems.
k. JMP, CALL, INT, RET and IRET instructions referring to another code segment will cause an exception 13 (general
protection violation) if an applicable privilege rule is violated.
l. An exception 13 fault occurs if CPL is greater than 0 (0 is the most privileged level).
m. An exception 13 fault occurs if CPL is greater than IOPL.
n. The IF bit of the flag register is not updated if CPL is greater than IOPL. The IOPL and VM fields of the flag register are
updated only if CPL
e
0.
o. The PE bit of the MSW (CR0) cannot be reset by this instruction. Use MOV into CR0 if desiring to reset the PE bit.
p. Any violation of privilege rules as applied to the selector operand does not cause a protection exception; rather, the zero
flag is cleared.
q. If the coprocessor’s memory operand violates a segment limit or segment access rights, an exception 13 fault (general
protection exception) will occur before the ESC instruction is executed. An exception 12 fault (stack segment limit violation
or not present) will occur if the stack limit is violated by the operand’s starting address.
r. The destination of a JMP, CALL, INT, RET or IRET must be in the defined limit of a code segment or an exception 13 fault
(general protection violation) will occur.
109
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