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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 71/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
use pipelined address with 16-bit memories then
BE0
Y
–BE3
Y
and W/R
Y
are also decoded to de-
termine when BS16
Y
should be asserted. See
5.4.3.6 Pipelined Address with Dynamic Data Bus
Sizing
.)
A2–A31 are directly usable for addressing 32-bit
and 16-bit devices. To address 16-bit devices, A1
and two byte enable signals are also needed.
To generate an A1 signal and two Byte Enable sig-
nals for 16-bit access, BE0
Y
–BE3
Y
should be de-
coded as in Table 5-7. Note certain combinations of
BE0
Y
–BE3
Y
are never generated by the Intel386
DX, leading to ‘‘don’t care’’ conditions in the decod-
er. Any BE0
Y
–BE3
Y
decoder, such as Figure 5-7,
may use the non-occurring BE0
Y
–BE3
Y
combina-
tions to its best advantage.
5.3.6 Operand Alignment
With the flexibility of memory addressing on the In-
tel386 DX, it is possible to transfer a logical operand
that spans more than one physical Dword or word of
memory
or
I/O.
Examples
are
32-bit
Dword
operands beginning at addresses not evenly divisi-
ble by 4, or a 16-bit word operand split between two
physical Dwords of the memory array.
Operand alignment and data bus size dictate when
multiple bus cycles are required. Table 5-8 describes
the transfer cycles generated for all combinations of
logical operand lengths, alignment, and data bus siz-
ing. When multiple bus cycles are required to trans-
fer a multi-byte logical operand, the highest-order
bytes are transferred first (but if BS16
Y
asserted
requires two 16-bit cycles be performed, that part of
the transfer is low-order first).
5.4 BUS FUNCTIONAL DESCRIPTION
5.4.1 Introduction
The Intel386 DX has separate, parallel buses for
data and address. The data bus is 32-bits in width,
and bidirectional. The address bus provides a 32-bit
value using 30 signals for the 30 upper-order ad-
dress bits and 4 Byte Enable signals to directly indi-
cate the active bytes. These buses are interpreted
and controlled via several associated definition or
control signals.
Table 5-7. Generating A1, BHE
Y
and BLE
Y
for Addressing 16-Bit Devices
Intel386
TM
DX Signals
16-Bit Bus Signals
Comments
BE3
Y
H
*
H
H
H
H
H
*
H
H
L
L
*
L
*
L
*
L
L
*
L
L
BE2
Y
H
*
H
H
H
L
L
*
L
L
H
H
*
H
*
H
*
L
L
*
L
L
BE1
Y
H
*
H
L
L
H
H
*
L
L
H
H
*
L
*
L
*
H
H
*
L
L
BE0
Y
H
*
L
H
L
H
L
*
H
L
H
L
*
H
*
L
*
H
L
*
H
L
A1
BHE
Y
BLE
Y
(A0)
x
L
L
L
H
x
L
L
H
x
x
x
H
x
L
L
x
H
L
L
H
x
L
L
L
x
x
x
L
x
L
L
x
L
H
L
L
x
H
L
H
x
x
x
L
x
H
L
xDno active bytes
xDnot contiguous bytes
xDnot contiguous bytes
xDnot contiguous bytes
xDnot contiguous bytes
xDnot continguous bytes
BLE
Y
asserted when D0–D7 of 16-bit bus is active.
BHE
Y
asserted when D8–D15 of 16-bit bus is active.
A1 low for all even words; A1 high for all odd words.
Key:
x
e
don’t care
H
e
high voltage level
L
e
low voltage level
*
e
a non-occurring pattern of Byte Enables; either none are asserted,
or the pattern has Byte Enables asserted for non-contiguous bytes
71
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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