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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 81/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
5.4.3.4 PIPELINED ADDRESS
Address pipelining is the option of requesting the
address and the bus cycle definition of the next, in-
ternally pending bus cycle before the current bus
cycle is acknowledged with READY
Y
asserted.
ADS
Y
is asserted by the Intel386 DX when the next
address is issued. The address pipelining option is
controlled on a cycle-by-cycle basis with the NA
Y
input signal.
Once a bus cycle is in progress and the current ad-
dress has been valid for at least one entire bus
state, the NA
Y
input is sampled at the end of every
phase one until the bus cycle is acknowledged. Dur-
ing non-pipelined bus cycles, therefore, NA
Y
is
sampled at the end of phase one in every T2. An
example is Cycle 2 in Figure 5-16, during which NA
Y
is sampled at the end of phase one of every T2 (it
was asserted once during the first T2 and has no
further effect during that bus cycle).
If NA
Y
is sampled asserted, the Intel386 DX is free
to drive the address and bus cycle definition of the
next bus cycle, and assert ADS
Y
, as soon as it has
a bus request internally pending. It may drive the
next address as early as the next bus state, whether
the current bus cycle is acknowledged at that time or
not.
Regarding the details of address pipelining, the In-
tel386 DX has the following characteristics:
1) For NA
Y
to be sampled asserted, BS16
Y
must
be negated at that sampling window (see Figure
5-16 Cycles 2 through 4, and Figure 5-17 Cycles 1
through 4). If NA
Y
and BS16
Y
are both sampled
asserted during the last T2 period of a bus cycle,
BS16
Y
asserted has priority. Therefore, if both
are asserted, the current bus size is taken to be
16 bits and the next address is not pipelined.
231630–20
Following any idle bus state (Ti), addresses are non-pipelined. Within non-pipelined bus cycles, NA
Y
is only sampled during wait states.
Therefore, to begin address pipelining during a group of non-pipelined bus cycles requires a non-pipelined cycle with at least one wait state
(Cycle 2 above).
Figure 5-16. Transitioning to Pipelined Address During Burst of Bus Cycles
81
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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