參數(shù)資料
型號(hào)： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁(yè)數(shù)： 46/139頁(yè)
文件大?。?/td> 1587K
代理商： INTEL386 DX
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Intel386
TM
DX MICROPROCESSOR
4.4 PROTECTION
4.4.1 Protection Concepts
231630–63
Figure 4-14. Four-Level Hierachical Protection
The Intel386 DX has four levels of protection which
are optimized to support the needs of a multi-tasking
operating system to isolate and protect user pro-
grams from each other and the operating system.
The privilege levels control the use of privileged in-
structions, I/O instructions, and access to segments
and segment descriptors. Unlike traditional micro-
processor-based systems where this protection is
achieved only through the use of complex external
hardware and software the Intel386 DX provides the
protection as part of its integrated Memory Manage-
ment Unit. The Intel386 DX offers an additional type
of protection on a page basis, when paging is en-
abled (See section 4.5.3
Page Level Protection
).
The four-level hierarchical privilege system is illus-
trated in Figure 4-14. It is an extension of the user/
supervisor privilege mode commonly used by mini-
computers and, in fact, the user/supervisor mode is
fully supported by the Intel386 DX paging mecha-
nism. The privilege levels (PL) are numbered 0
through 3. Level 0 is the most privileged or trusted
level.
4.4.2 Rules of Privilege
The Intel386 DX controls access to both data and
procedures between levels of a task, according to
the following rules.
#
Data stored in a segment with privilege level
p
can
be accessed only by code executing at a privilege
level at least as privileged as
p
.
#
A code segment/procedure with privilege level
p
can only be called by a task executing at the same
or a lesser privilege level than
p
.
4.4.3 Privilege Levels
4.4.3.1 TASK PRIVILEGE
At any point in time, a task on the Intel386 DX al-
ways executes at one of the four privilege levels.
The Current Privilege Level (CPL) specifies the
task’s privilege level. A task’s CPL may only be
changed by control transfers through gate descrip-
tors to a code segment with a different privilege lev-
el. (See section 4.4.4
Privilege Level Transfers
)
Thus, an application program running at PL
e
3 may
call an operating system routine at PL
e
1 (via a
gate) which would cause the task’s CPL to be set to
1 until the operating system routine was finished.
4.4.3.2 SELECTOR PRIVILEGE (RPL)
The privilege level of a selector is specified by the
RPL field. The RPL is the two least significant bits of
the selector. The selector’s RPL is only used to es-
tablish a less trusted privilege level than the current
privilege level for the use of a segment. This level is
called the task’s effective privilege level (EPL). The
EPL is defined as being the least privileged (i.e. nu-
merically larger) level of a task’s CPL and a selec-
tor’s RPL. Thus, if selector’s RPL
e
0 then the CPL
always specifies the privilege level for making an ac-
cess using the selector. On the other hand if RPL
e
3 then a selector can only access segments at level
3 regardless of the task’s CPL. The RPL is most
commonly used to verify that pointers passed to an
operating system procedure do not access data that
is of higher privilege than the procedure that origi-
nated the pointer. Since the originator of a selector
can specify any RPL value, the Adjust RPL (ARPL)
instruction is provided to force the RPL bits to the
originator’s CPL.
4.4.3.3 I/O PRIVILEGE AND I/O PERMISSION
BITMAP
The I/O privilege level (IOPL, a 2-bit field in the
EFLAG register) defines the least privileged level at
which I/O instructions can be unconditionally per-
formed. I/O instructions can be unconditionally per-
formed when CPL
s
IOPL. (The I/O instructions are
IN, OUT, INS, OUTS, REP INS, and REP OUTS.)
When CPL
l
IOPL, and the current task is associat-
ed with a 286 TSS, attempted I/O instructions cause
an exception 13 fault. When CPL
l
IOPL, and the
current task is associated with an Intel386 DX TSS,
the I/O Permission Bitmap (part of an Intel386 DX
TSS) is consulted on whether I/O to the port is al-
lowed, or an exception 13 fault is to be generated
46
相關(guān)PDF資料
PDF描述
Intel386 EX Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
INTEL386 SXSA 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器)
intel386 SX 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
INTEL386 Intel386 EX Embedded Microprocessor
Intel387 dx DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
INTEL386SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR
INTEL387 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR
INTEL387DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR
INTEL387SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR
INTEL387TMDX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR
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