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參數資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數： | 85/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
Bus States:
T1Dfirst clock of a non-pipelined bus cycle (Intel386 DX drives new ad-
dress and asserts ADS
Y
).
T2Dsubsequent clocks of a bus cycle when NA
Y
has not been sampled
asserted in the current bus cycle.
T2IDsubsequent clocks of a bus cycle when NA
Y
has been sampled as-
serted in the current bus cycle but there is not yet an internal bus request
pending (Intel386 DX will not drive new address or assert ADS
Y
).
T2PDsubsequent clocks of a bus cycle when NA
Y
has been sampled
asserted in the current bus cycle and there is an internal bus request pend-
ing (Intel386 DX drives new address and asserts ADS
Y
).
T1PDfirst clock of a pipelined bus cycle.
TiDidle state.
ThDhold acknowledge state (Intel386 DX asserts HLDA).
Asserting NA
Y
for pipelined address gives access to three more bus
states: T2I, T2P and T1P.
Using pipelined address, the fastest bus cycle consists of T1P and T2P.
231630–24
Figure 5-20. Intel386
TM
DX Complete Bus States (including pipelined address)
Realistically, address pipelining is almost always
maintained as long as NA
Y
is sampled asserted.
This is so because in the absence of any other re-
quest, a code prefetch request is always internally
pending until the instruction decoder and code pre-
fetch queue are completely full. Therefore address
pipelining is maintained for long bursts of bus cycles,
if the bus is available (i.e., HOLD negated) and NA
Y
is sampled asserted in each of the bus cycles.
5.4.3.6 PIPELINED ADDRESS WITH DYNAMIC
DATA BUS SIZING
The BS16
Y
feature allows easy interface to 16-bit
data buses. When asserted, the Intel386 DX bus
interface hardware performs appropriate action to
make the transfer using a 16-bit data bus connected
on D0–D15.
There is a degree of interaction, however, between
the use of Address Pipelining and the use of Bus
Size 16. The interaction results from the multiple bus
cycles required when transferring 32-bit operands
over a 16-bit bus. If the operand requires both 16-bit
halves of the 32-bit bus, the appropriate Intel386 DX
action is a second bus cycle to complete the oper-
and’s transfer. It is this necessity that conflicts with
NA
Y
usage.
When NA
Y
is sampled asserted, the Intel386 DX
commits
itself
to
perform
the
next
inter-
85
相關PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內部數據總線和24位內部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數學協處理器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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