參數(shù)資料
型號： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理）
文件頁數(shù)： 97/139頁
文件大?。?/td> 1587K
代理商： INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
Table 6-1. Intel386
TM
DX Instruction Set Clock Count Summary
(Continued)
CLOCK COUNT
NOTES
Real
Address
Mode or
Virtual
8086
Mode
Real
Address
Mode or
Virtual
8086
Mode
INSTRUCTION
FORMAT
Protected
Virtual
Address
Mode
Protected
Virtual
Address
Mode
SEGMENT CONTROL
LDS
e
Load Pointer to DS
1 1 0 0 0 1 0 1
mod reg
r/m
7
22
b
h, i, j
LES
e
Load Pointer to ES
1 1 0 0 0 1 0 0
mod reg
r/m
7
22
b
h, i, j
LFS
e
Load Pointer to FS
0 0 0 0 1 1 1 1
1 0 1 1 0 1 0 0
mod reg
r/m
7
25
b
h, i, j
LGS
e
Load Pointer to GS
0 0 0 0 1 1 1 1
1 0 1 1 0 1 0 1
mod reg
r/m
7
25
b
h, i, j
LSS
e
Load Pointer to SS
0 0 0 0 1 1 1 1
1 0 1 1 0 0 1 0
mod reg
r/m
7
22
b
h, i, j
FLAG CONTROL
CLC
e
Clear Carry Flag
1 1 1 1 1 0 0 0
2
2
CLD
e
Clear Direction Flag
1 1 1 1 1 1 0 0
2
2
CLI
e
Clear Interrupt Enable Flag
1 1 1 1 1 0 1 0
8
8
m
CLTS
e
Clear Task Switched Flag
0 0 0 0 1 1 1 1
0 0 0 0 0 1 1 0
6
6
c
l
CMC
e
Complement Carry Flag
1 1 1 1 0 1 0 1
2
2
LAHF
e
Load AH into Flag
1 0 0 1 1 1 1 1
2
2
POPF
e
Pop Flags
1 0 0 1 1 1 0 1
5
5
b
h, n
PUSHF
e
Push Flags
1 0 0 1 1 1 0 0
4
4
b
h
SAHF
e
Store AH into Flags
1 0 0 1 1 1 1 0
3
3
STC
e
Set Carry Flag
1 1 1 1 1 0 0 1
2
2
STD
e
Set Direction Flag
1 1 1 1 1 1 0 1
2
2
STI
e
Set Interrupt Enable Flag
1 1 1 1 1 0 1 1
8
8
m
ARITHMETIC
ADD
e
Add
Register to Register
0 0 0 0 0 0 d w
mod reg
r/m
2
2
Register to Memory
0 0 0 0 0 0 0 w
mod reg
r/m
7
7
b
h
Memory to Register
0 0 0 0 0 0 1 w
mod reg
r/m
6
6
b
h
Immediate to Register/Memory
1 0 0 0 0 0 s w
mod 0 0 0
r/m
immediate data
2/7
2/7
b
h
Immediate to Accumulator (short form)
0 0 0 0 0 1 0 w
immediate data
2
2
ADC
e
Add With Carry
Register to Register
0 0 0 1 0 0 d w
mod reg
r/m
2
2
Register to Memory
0 0 0 1 0 0 0 w
mod reg
r/m
7
7
b
h
Memory to Register
0 0 0 1 0 0 1 w
mod reg
r/m
6
6
b
h
Immediate to Register/Memory
1 0 0 0 0 0 s w
mod 0 1 0
r/m
immediate data
2/7
2/7
b
h
Immediate to Accumulator (short form)
0 0 0 1 0 1 0 w
immediate data
2
2
INC
e
Increment
Register/Memory
1 1 1 1 1 1 1 w
mod 0 0 0
r/m
2/6
2/6
b
h
Register (short form)
0 1 0 0 0
reg
2
2
SUB
e
Subtract
Register from Register
0 0 1 0 1 0 d w
mod reg
r/m
2
2
97
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