參數(shù)資料
型號： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁數(shù)： 63/139頁
文件大小： 1587K
代理商： INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
transfers automatically generated for Intel386 DX-to-
coprocessor communication use I/O addresses
800000F8H through 800000FFH, so A31 HIGH in
conjunction with M/IO
Y
LOW allows simple genera-
tion of the coprocessor select signal.
The Byte Enable outputs, BE0
Y
–BE3
Y
, directly in-
dicate which bytes of the 32-bit data bus are in-
volved with the current transfer. This is most conve-
nient for external hardware.
BE0
Y
applies to D0–D7
BE1
Y
applies to D8–D15
BE2
Y
applies to D16–D23
BE3
Y
applies to D24–D31
The number of Byte Enables asserted indicates the
physical size of the operand being transferred (1, 2,
3, or 4 bytes). Refer to section
5.3.6 Operand Align-
ment
.
When a memory write cycle or I/O write cycle is in
progress, and the operand being transferred occu-
pies
only
the upper 16 bits of the data bus (D16–
D31), duplicate data is simultaneously presented on
the corresponding lower 16-bits of the data bus
(D0–D15). This duplication is performed for optimum
write performance on 16-bit buses. The pattern of
write data duplication is a function of the Byte En-
ables asserted during the write cycle. Table 5-1 lists
the write data present on D0–D31, as a function of
the asserted Byte Enable outputs BE0
Y
–BE3
Y
.
5.2.5 Bus Cycle Definition Signals
(W/R
Y
, D/C
Y
, M/IO
Y
, LOCK
Y
)
These three-state outputs define the type of bus cy-
cle being performed. W/R
Y
distinguishes between
write and read cycles. D/C
Y
distinguishes between
data and control cycles. M/IO
Y
distinguishes be-
tween memory and I/O cycles. LOCK
Y
distin-
guishes between locked and unlocked bus cycles.
The primary bus cycle definition signals are W/R
Y
,
D/C
Y
and M/IO
Y
, since these are the signals driv-
en valid as the ADS
Y
(Address Status output) is
driven asserted. The LOCK
Y
is driven valid at the
same time as the first locked bus cycle begins,
which due to address pipelining, could be later than
ADS
Y
is driven asserted. See
5.4.3.4 Pipelined Ad-
dress.
The LOCK
Y
is negated when the READY
Y
input terminates the last bus cycle which was
locked.
Exact bus cycle definitions, as a function of W/R
Y
,
D/C
Y
, and M/IO
Y
, are given in Table 5-2. Note one
combination of W/R
Y
, D/C
Y
and M/IO
Y
is never
given when ADS
Y
is asserted (however, that combi-
nation, which is listed as ‘‘does not occur,’’ may oc-
cur during
idle
bus states when ADS
Y
is
not
assert-
ed). If M/IO
Y
, D/C
Y
, and W/R
Y
are qualified by
ADS
Y
asserted, then a decoding scheme may be
simplified by using this definition of the ‘‘does not
occur’’ combination.
Table 5-1. Write Data Duplication as a Function of BE0
Y
–BE3
Y
Intel386
TM
DX Byte Enables
Intel386
TM
DX Write Data
Automatic
Duplication
BE3
Y
BE2
Y
BE1
Y
BE0
Y
D24–D31
D16–D23
D8–D15
D0–D7
High
High
High
Low
High
High
Low
High
High
Low
High
High
Low
High
High
High
undef
undef
undef
D
undef
undef
C
undef
undef
B
undef
D
A
No
No
Yes
Yes
undef
C
undef
High
High
Low
High
Low
Low
Low
Low
High
Low
High
High
undef
undef
D
undef
C
C
B
B
D
A
No
No
Yes
undef
C
High
Low
Low
Low
Low
Low
Low
High
undef
D
C
C
B
B
A
No
No
undef
Low
Low
Low
Low
D
C
B
A
No
Key:
D
e
logical write data d24–d31
C
e
logical write data d16–d23
B
e
logical write data d8–d15
A
e
logical write data d0–d7
63
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