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參數(shù)資料
| 型號(hào)： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理） |
| 文件頁數(shù)： | 74/139頁 |
| 文件大小： | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
The fastest Intel386 DX bus cycle requires only two
bus states. For example, three consecutive bus read
cycles, each consisting of two bus states, are shown
by Figure 5-8. The bus states in each cycle are
named
T1
and
T2
. Any memory or I/O address may
be accessed by such a two-state bus cycle, if the
external hardware is fast enough. The high-band-
width, two-clock bus cycle realizes the full potential
of fast main memory, or cache memory.
Every bus cycle continues until it is acknowledged
by the external system hardware, using the Intel386
DX READY
Y
input. Acknowledging the bus cycle at
the end of the first T2 results in the shortest bus
cycle, requiring only T1 and T2. If READY
Y
is not
immediately asserted, however, T2 states are re-
peated indefinitely until the READY
Y
input is sam-
pled asserted.
5.4.2 Address Pipelining
The address pipelining option provides a choice of
bus cycle timings. Pipelined or non-pipelined ad-
dress timing is selectable on a cycle-by-cycle basis
with the Next Address (NA
Y
) input.
When address pipelining is not selected, the current
address and bus cycle definition remain stable
throughout the bus cycle.
When address pipelining is selected, the address
(BE0
Y
–BE3
Y
, A2–A31) and definition (W/R
Y
,
D/C
Y
and M/IO
Y
) of the next cycle are available
before the end of the current cycle. To signal their
availability, the Intel386 DX address status output
(ADS
Y
) is also asserted. Figure 5-9 illustrates the
fastest read cycles with pipelined address timing.
Note from Figure 5-9 the fastest bus cycles using
pipelined address require only two bus states,
named
T1P
and
T2P
. Therefore cycles with pipe-
lined address timing allow the same data bandwidth
as non-pipelined cycles, but address-to-data access
time is increased compared to that of a non-pipe-
lined cycle.
By increasing the address-to-data access time, pipe-
lined address timing reduces wait state require-
ments. For example, if one wait state is required with
non-pipelined address timing, no wait states would
be required with pipelined address.
231630–12
Fastest pipelined bus cycles consist of T1P and T2P
Figure 5-9. Fastest Read Cycles with Pipelined Address Timing
74
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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