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| 型號(hào)： | intel386 DX |
| 廠(chǎng)商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理） |
| 文件頁(yè)數(shù)： | 87/139頁(yè) |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
Certain types of 16-bit or 8-bit operands require no
adjustment for correct transfer on a 16-bit bus.
Those are read or write operands using only the low-
er half of the data bus, and write operands using
only the upper half of the bus since the Intel386 DX
simultaneously duplicates the write data on the low-
er half of the data bus. For these patterns of Byte
Enables and the R/W
Y
signals, BS16
Y
need not be
asserted at the Intel386 DX allowing NA
Y
to be as-
serted during the bus cycle if desired.
5.4.4 Interrupt Acknowledge (INTA)
Cycles
In response to an interrupt request on the INTR in-
put when interrupts are enabled, the Intel386 DX
performs two interrupt acknowledge cycles. These
bus cycles are similar to read cycles in that bus defi-
nition signals define the type of bus activity taking
place, and each cycle continues until acknowledged
by READY
Y
sampled asserted.
The state of A2 distinguishes the first and second
interrupt acknowledge cycles. The byte address
driven during the first interrupt acknowledge cycle is
4 (A31–A3 low, A2 high, BE3
Y
–BE1
Y
high, and
BE0
Y
low). The address driven during the second
interrupt acknowledge cycle is 0 (A31–A2 low,
BE3
Y
–BE1
Y
high, BE0
Y
low).
231630–26
Interrupt Vector (0–255) is read on D0–D7 at end of second Interrupt Acknowledge bus cycle.
Because each Interrupt Acknowledge bus cycle is followed by idle bus states, asserting NA
Y
has no practical effect. Choose the approach
which is simplest for your system hardware design.
Figure 5-22. Interrupt Acknowledge Cycles
87
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線(xiàn)和24位內(nèi)部地址總線(xiàn)32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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