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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 9/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
GENERAL DATA AND ADDRESS REGISTERS
31
16 15
0
AX
EAX
BX
EBX
CX
ECX
DX
EDX
SI
ESI
DI
EDI
GS
*
BP
EBP
SP
ESP
SEGMENT SELECTOR REGISTERS
15
0
CS
CODE
SS
STACK
DS
ES
DATA
FS
INSTRUCTION POINTER
AND FLAGS REGISTER
31
16 15
0
IP
EIP
FLAGS
EFLAGS
Figure 2-1. Intel386
TM
DX Base
Architecture Registers
The selectors are also task-specific, so the segment
registers are automatically loaded with new context
upon a task switch operation.
The other types of registers, Control, System Ad-
dress, Debug, and Test, are primarily used by sys-
tem software.
2.3 REGISTER DESCRIPTIONS
2.3.1 General Purpose Registers
General Purpose Registers:
The eight general pur-
pose registers of 32 bits hold data or address quanti-
ties. The general registers, Figure 2-2, support data
operands of 1, 8, 16, 32 and 64 bits, and bit fields of
1 to 32 bits. They support address operands of 16
and 32 bits. The 32-bit registers are named EAX,
EBX, ECX, EDX, ESI, EDI, EBP, and ESP.
The least significant 16 bits of the registers can be
accessed separately. This is done by using the 16-
bit names of the registers AX, BX, CX, DX, SI, DI,
BP, and SP. When accessed as a 16-bit operand,
the upper 16 bits of the register are neither used nor
changed.
Finally 8-bit operations can individually access the
lowest byte (bits 0–7) and the higher byte (bits 8–
15) of general purpose registers AX, BX, CX and DX.
The lowest bytes are named AL, BL, CL and DL,
respectively. The higher bytes are named AH, BH,
CH and DH, respectively. The individual byte acces-
sibility offers additional flexibility for data operations,
but is not used for effective address calculation.
31
16
15
8
7
0
AH A X
AL
EAX
BH B X
BL
EBX
CH C X
CL
ECX
DH D X
DL
EDX
SI
ESI
DI
EDI
BP
EBP
SP
ESP
31
16
15
0
EIP
X
IP
Y
Figure 2-2. General Registers
and Instruction Pointer
2.3.2 Instruction Pointer
The instruction pointer, Figure 2-2, is a 32-bit regis-
ter named EIP. EIP holds the offset of the next in-
struction to be executed. The offset is always rela-
tive to the base of the code segment (CS). The low-
er 16 bits (bits 0–15) of EIP contain the 16-bit in-
struction pointer named IP, which is used by 16-bit
addressing.
2.3.3 Flags Register
The Flags Register is a 32-bit register named
EFLAGS. The defined bits and bit fields within
EFLAGS, shown in Figure 2-3, control certain opera-
tions and indicate status of the Intel386 DX. The
lower 16 bits (bit 0–15) of EFLAGS contain the
16-bit flag register named FLAGS, which is most
useful when executing 8086 and 80286 code.
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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