參數(shù)資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內(nèi)存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數(shù): 94/139頁
文件大小: 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
5.8 COPROCESSOR INTERFACING
The Intel386 DX provides an automatic interface for
the Intel Intel387 DX numeric floating-point coproc-
essor. The Intel387 DX coprocessor uses an I/O-
mapped interface driven automatically by the In-
tel386 DX and assisted by three dedicated signals:
BUSY
Y
, ERROR
Y
, and PEREQ.
As the Intel386 DX begins supporting a coprocessor
instruction, it tests the BUSY
Y
and ERROR
Y
sig-
nals to determine if the coprocessor can accept its
next instruction. Thus, the BUSY
Y
and ERROR
Y
inputs eliminate the need for any ‘‘preamble’’ bus
cycles for communication between processor and
coprocessor. The Intel387 DX can be given its com-
mand opcode immediately. The dedicated signals
provide instruction synchronization, and eliminate
the need of using the Intel386 DX WAIT opcode
(9Bh) for Intel387 DX coprocessor instruction syn-
chronization (the WAIT opcode was required when
8086 or 8088 was used with the 8087 coprocessor).
Custom coprocessors can be included in Intel386
DX-based systems, via memory-mapped or I/O-
mapped interfaces. Such coprocessor interfaces al-
low a completely custom protocol, and are not limit-
ed to a set of coprocessor protocol ‘‘primitives’’. In-
stead, memory-mapped or I/O-mapped interfaces
may use all applicable Intel386 DX instructions for
high-speed
coprocessor
BUSY
Y
and ERROR
Y
inputs of the Intel386 DX
may also be used for the custom coprocessor inter-
face, if such hardware assist is desired. These sig-
nals can be tested by the Intel386 DX WAIT opcode
(9Bh). The WAIT instruction will wait until the
BUSY
Y
input is negated (interruptable by an NMI or
enabled INTR input), but generates an exception 16
fault if the ERROR
Y
pin is in the asserted state
when the BUSY
Y
goes (or is) negated. If the custom
coprocessor interface is memory-mapped, protec-
tion of the addresses used for the interface can be
provided with the Intel386 DX on-chip paging or
communication.
The
segmentation mechanisms. If the custom interface
is I/O-mapped, protection of the interface can be
provided with the Intel386 DX IOPL (I/O Privilege
Level) mechanism.
The Intel387 DX numeric coprocessor interface is
I/O mapped as shown in Table 5-11. Note that the
Intel387 DX coprocessor interface addresses are
beyond the 0h-FFFFh range for programmed I/O.
When the Intel386 DX supports the Intel387 DX co-
processor, the Intel386 DX automatically generates
bus cycles to the coprocessor interface addresses.
Table 5-11. Numeric Coprocessor
Port Addresses
Address in
Intel386
TM
DX
I/O Space
Intel387
TM
DX
Coprocessor
Register
800000F8h
Opcode Register
(32-bit port)
800000FCh
Operand Register
(32-bit port)
To correctly map the Intel387 DX coprocessor regis-
ters to the appropriate I/O addresses, connect the
Intel387 DX coprocessor CMD0
Y
pin directly to the
A2 output of the Intel386 DX.
5.8.1 Software Testing for
Coprocessor Presence
When software is used to test for coprocessor (In-
tel387 DX) presence, it should use only the following
coprocessor opcodes: FINIT, FNINIT, FSTCW mem,
FSTSW mem, FSTSW AX. To use other coproces-
sor opcodes when a coprocessor is known to be not
present, first set EM
e
1 in Intel386 DX CR0.
94
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