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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 77/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
At the end of the second bus state within the bus
cycle, READY
Y
is sampled. At that time, if external
hardware acknowledges the bus cycle by asserting
READY
Y
, the bus cycle terminates as shown in Fig-
ure 5-11. If READY
Y
is negated as in Figure 5-12,
the cycle continues another bus state (a wait state)
and READY
Y
is sampled again at the end of that
state. This continues indefinitely until the cycle is ac-
knowledged by READY
Y
asserted.
When the current cycle is acknowledged, the In-
tel386 DX terminates it. When a read cycle is ac-
knowledged, the Intel386 DX latches the information
present at its data pins. When a write cycle is ac-
knowledged, the Intel386 DX write data remains val-
id throughout phase one of the next bus state, to
provide write data hold time.
5.4.3.2 NON-PIPELINED ADDRESS
Any bus cycle may be performed with non-pipelined
address timing. For example, Figure 5-11 shows a
mixture of read and write cycles with non-pipelined
address timing. Figure 5-11 shows the fastest possi-
ble cycles with non-pipelined address have two bus
states per bus cycle. The states are named T1 and
T2. In phase one of the T1, the address signals and
bus cycle definition signals are driven valid, and to
signal their availability, address status (ADS
Y
) is
simultaneously asserted.
During read or write cycles, the data bus behaves as
follows. If the cycle is a read, the Intel386 DX floats
its data signals to allow driving by the external de-
vice being addressed.
The Intel386 DX requires
that all data bus pins be at a valid logic state
(high or low) at the end of each read cycle, when
READY
Y
is asserted, even if all byte enables are
not asserted. The system MUST be designed to
meet this requirement.
If the cycle is a write, data
signals are driven by the Intel386 DX beginning in
phase two of T1 until phase one of the bus state
following cycle acknowledgment.
Figure 5-12 illustrates non-pipelined bus cycles with
one wait added to cycles 2 and 3. READY
Y
is sam-
pled negated at the end of the first T2 in cycles 2
and 3. Therefore cycles 2 and 3 have T2 repeated.
At the end of the second T2, READY
Y
is sampled
asserted.
231630–16
Idle states are shown here for diagram variety only. Write cycles are
not
always followed by an idle state. An active bus cycle can immediately
follow the write cycle.
Figure 5-12. Various Bus Cycles and Idle States with Non-Pipelined Address
(various number of wait states)
77
相關PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內部數(shù)據(jù)總線和24位內部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學協(xié)處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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