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| 型號(hào)： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理） |
| 文件頁(yè)數(shù)： | 61/139頁(yè) |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
ue of ESP stored in step 4 is used. Since VM
e
1,
these are done as 8086 segment register loads.
Else if VM
e
0, check that the selectors in ES,
DS, FS, and GS are valid in the interrupted rou-
tine. Null out invalid selectors to trap if an at-
tempt is made to access through them.
l
CPL), pop the stack pointer
SS:ESP from the stack. The ESP register is
popped first, followed by 32-bits containing SS in
the lower 16 bits. If VM
e
0, SS is loaded as a
protected mode segment register load. If VM
e
1,
an 8086 segment register load is used.
(6) If (RPL(CS)
(7) Resume execution of the interrupted routine. The
VM bit in the FLAGS register (restored from the
interrupt routine’s stack image in step 1) deter-
mines whether the processor resumes the inter-
rupted routine in Protected mode of Virtual 8086
mode.
5. FUNCTIONAL DATA
5.1 INTRODUCTION
The Intel386 DX features a straightforward function-
al interface to the external hardware. The Intel386
DX has separate, parallel buses for data and ad-
dress. The data bus is 32-bits in width, and bidirec-
tional. The address bus outputs 32-bit address val-
ues in the most directly usable form for the high-
speed local bus: 4 individual byte enable signals,
and the 30 upper-order bits as a binary value. The
data and address buses are interpreted and con-
trolled with their associated control signals.
A
dynamic data bus sizing
feature allows the proc-
essor to handle a mix of 32- and 16-bit external bus-
es on a cycle-by-cycle basis (see
5.3.4 Data Bus
Sizing
). If 16-bit bus size is selected, the Intel386
DX automatically makes any adjustment needed,
even performing another 16-bit bus cycle to com-
plete the transfer if that is necessary. 8-bit peripheral
devices may be connected to 32-bit or 16-bit buses
with no loss of performance. A
new address pipe-
lining option
is provided and applies to 32-bit and
16-bit buses for substantially improved memory utili-
zation, especially for the most heavily used memory
resources.
The
address pipelining option
, when selected, typ-
ically allows a given memory interface to operate
with one less wait state than would otherwise be
required (see
5.4.2 Address Pipelining
). The pipe-
lined bus is also well suited to interleaved memory
designs. When address pipelining is requested by
the external hardware, the Intel386 DX will output
the address and bus cycle definition of the next bus
cycle (if it is internally available) even while waiting
for the current cycle to be acknowledged.
Non-pipelined address timing, however, is ideal for
external cache designs, since the cache memory will
typically be fast enough to allow non-pipelined cy-
cles. For maximum design flexibility, the address
pipelining option is selectable on a cycle-by-cycle
basis.
The processor’s bus cycle is the basic mechanism
for information transfer, either from system to proc-
essor, or from processor to system. Intel386 DX bus
cycles perform data transfer in a minimum of only
two clock periods. On a 32-bit data bus, the maxi-
mum Intel386 DX transfer bandwidth at 20 MHz is
therefore 40 MBytes/sec, at 25 MHz bandwidth, is
50 Mbytes/sec, and at 33 MHz bandwidth, is
66 Mbytes/sec. Any bus cycle will be extended for
more than two clock periods, however, if external
hardware withholds acknowledgement of the cycle.
At the appropriate time, acknowledgement is sig-
nalled by asserting the Intel386 DX READY
Y
input.
The Intel386 DX can relinquish control of its local
buses to allow mastership by other devices, such as
direct memory access channels. When relinquished,
HLDA is the only output pin driven by the Intel386
DX providing near-complete isolation of the proces-
sor from its system. The near-complete isolation
characteristic is ideal when driving the system from
test equipment, and in fault-tolerant applications.
Functional data covered in this chapter describes
the processor’s hardware interface. First, the set of
signals available at the processor pins is described
(see
5.2 Signal Description
). Following that are the
signal waveforms occurring during bus cycles (see
5.3 Bus Transfer Mechanism
,
5.4 Bus Functional
Description
and
5.5 Other Functional Descrip-
tions
).
5.2 SIGNAL DESCRIPTION
5.2.1 Introduction
Ahead is a brief description of the Intel386 DX input
and output signals arranged by functional groups.
Note the
Y
symbol at the end of a signal name indi-
cates the active, or asserted, state occurs when the
signal is at a low voltage. When no
Y
is present after
the signal name, the signal is asserted when at the
high voltage level.
Example signal: M/IO
Y
D High voltage indicates
Memory selected
D Low
I/O selected
voltage
indicates
61
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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