參數資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數: 123/139頁
文件大?。?/td> 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
9. ELECTRICAL DATA
9.1 INTRODUCTION
The following sections describe recommended elec-
trical connections for the Intel386 DX, and its electri-
cal specifications.
9.2 POWER AND GROUNDING
9.2.1 Power Connections
The Intel386 DX is implemented in CHMOS III and
CHMOS IV technology and has modest power re-
quirements. However, its high clock frequency and
72 output buffers (address, data, control, and HLDA)
can cause power surges as multiple output buffers
drive new signal levels simultaneously. For clean on-
chip power distribution at high frequency, 20 V
CC
and 21 V
SS
pins separately feed functional units of
the Intel386 DX.
Power and ground connections must be made to all
external V
CC
and GND pins of the Intel386 DX. On
the circuit board, all V
CC
pins must be connected on
a V
CC
plane. All V
SS
pins must be likewise connect-
ed on a GND plane.
9.2.2 Power Decoupling
Recommendations
Liberal decoupling capacitance should be placed
near the Intel386 DX. The Intel386 DX driving its
32-bit parallel address and data buses at high fre-
quencies can cause transient power surges, particu-
larly when driving large capacitive loads.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical per-
formance. Inductance can be reduced by shortening
circuit board traces between the Intel386 DX and
decoupling capacitors as much as possible. Capaci-
tors specifically for PGA packages are also commer-
cially available, for the lowest possible inductance.
9.2.3 Resistor Recommendations
The ERROR
Y
and BUSY
Y
inputs have resistor pull-
ups of approximately 20 K
X
built-in to the Intel386
DX to keep these signals negated when no Intel387
DX coprocessor is present in the system (or tempo-
rarily removed from its socket). The BS16
Y
input
also has an internal pullup resistor of approximately
20 K
X
, and the PEREQ input has an internal pull-
down resistor of approximately 20 K
X
.
In typical designs, the external pullup resistors
shown in Table 9-1 are recommended. However, a
particular design may have reason to adjust the re-
sistor values recommended here, or alter the use of
pullup resistors in other ways.
9.2.4 Other Connection
Recommendations
For reliable operation, always connect unused in-
puts to an appropriate signal level. N.C. pins should
always remain unconnected.
Particularly when not using interrupts or bus hold,
(as when first prototyping, perhaps) prevent any
chance of spurious activity by connecting these as-
sociated inputs to GND:
Pin
Signal
B7
B8
D14
INTR
NMI
HOLD
If not using address pipelining, pullup D13 NA
Y
to
V
CC
.
If not using 16-bit bus size, pullup C14 BS16
Y
to
V
CC
.
Pullups in the range of 20 K
X
are recommended.
Table 9-1. Recommended Resistor Pullups to V
CC
Pin and Signal
Pullup Value
Purpose
E14
ADS
Y
20 K
X
g
10%
Lightly Pull ADS
Y
Negated
During Intel386 DX Hold
Acknowledge States
C10
LOCK
Y
20 K
X
g
10%
Lightly Pull LOCK
Y
Negated
During Intel386 DX Hold
Acknowledge States
123
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