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| 型號(hào)： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理） |
| 文件頁(yè)數(shù)： | 53/139頁(yè) |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
structure of a program. While segment selectors can
be considered the logical ‘‘name’’ of a program
module or data structure, a page most likely corre-
sponds to only a portion of a module or data struc-
ture.
By taking advantage of the locality of reference dis-
played by most programs, only a small number of
pages from each active task need be in memory at
any one moment.
4.5.2 Paging Organization
4.5.2.1 PAGE MECHANISM
The Intel386 DX uses two levels of tables to trans-
late the linear address (from the segmentation unit)
into a physical address. There are three compo-
nents to the paging mechanism of the Intel386 DX:
the page directory, the page tables, and the page
itself (page frame). All memory-resident elements of
the Intel386 DX paging mechanism are the same
size, namely, 4K bytes. A uniform size for all of the
elements simplifies memory allocation and realloca-
tion schemes, since there is no problem with memo-
ry fragmentation. Figure 4-19 shows how the paging
mechanism works.
4.5.2.2 PAGE DESCRIPTOR BASE REGISTER
CR2 is the Page Fault Linear Address register. It
holds the 32-bit linear address which caused the last
page fault detected.
CR3 is the Page Directory Physical Base Address
Register. It contains the physical starting address of
the Page Directory. The lower 12 bits of CR3 are
always zero to ensure that the Page Directory is al-
ways page aligned. Loading it via a MOV CR3, reg
instruction causes the Page Table Entry cache to be
flushed, as will a task switch through a TSS which
changes
the value of CR0. (See 4.5.4
Translation
Lookaside Buffer
).
4.5.2.3 PAGE DIRECTORY
The Page Directory is 4K bytes long and allows up to
1024 Page Directory Entries. Each Page Directory
Entry contains the address of the next level of ta-
bles, the Page Tables and information about the
page table. The contents of a Page Directory Entry
are shown in Figure 4-20. The upper 10 bits of the
linear address (A22–A31) are used as an index to
select the correct Page Directory Entry.
231630–67
Figure 4-19. Paging Mechanism
31
12
11
10
9
8
7
6
5
4
3
2
1
0
OS
RESERVED
U
D
S
R
D
W
PAGE TABLE ADDRESS 31..12
0
0
D
A
0
0
P
Figure 4-20. Page Directory Entry (Points to Page Table)
53
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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