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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 73/139頁 |
| 文件大小： | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
The definition of each bus cycle is given by three
definition signals: M/IO
Y
, W/R
Y
and D/C
Y
. At the
same time, a valid address is present on the byte
enable signals BE0
Y
–BE3
Y
and other address sig-
nals A2–A31. A status signal, ADS
Y
, indicates
when the Intel386 DX issues a new bus cycle defini-
tion and address.
Collectively, the address bus, data bus and all asso-
ciated control signals are referred to simply as ‘‘the
bus’’.
When active, the bus performs one of the bus cycles
below:
1) read from memory space
2) locked read from memory space
3) write to memory space
4) locked write to memory space
5) read from I/O space (or coprocessor)
6) write to I/O space (or coprocessor)
7) interrupt acknowledge
8) indicate halt, or indicate shutdown
Table 5-2 shows the encoding of the bus cycle defi-
nition signals for each bus cycle. See section
5.2.5
Bus Cycle Definition
.
The data bus has a dynamic sizing feature support-
ing 32- and 16-bit bus size. Data bus size is indicated
to the Intel386 DX using its Bus Size 16 (BS16
Y
)
input. All bus functions can be performed with either
data bus size.
When the Intel386 DX bus is not performing one of
the activities listed above, it is either Idle or in the
Hold Acknowledge state, which may be detected by
external circuitry. The idle state can be identified by
the Intel386 DX giving no further assertions on its
address strobe output (ADS
Y
) since the beginning
of its most recent bus cycle, and the most recent
bus cycle has been terminated. The hold acknowl-
edge state is identified by the Intel386 DX asserting
its hold acknowledge (HLDA) output.
The shortest time unit of bus activity is a bus state. A
bus state is one processor clock period (two CLK2
periods) in duration. A complete data transfer occurs
during a bus cycle, composed of two or more bus
states.
231630–11
Fastest non-pipelined bus cycles consist of T1 and T2
Figure 5-8. Fastest Read Cycles with Non-Pipelined Address Timing
73
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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