參數(shù)資料
型號(hào)： MT29F4G08BABWP
元件分類(lèi)： PROM
英文描述： 512M X 8 FLASH 2.7V PROM, 18 ns, PDSO48
封裝： LEAD FREE, TSOP1-48
文件頁(yè)數(shù)： 8/57頁(yè)
文件大?。?/td> 1057K
代理商： MT29F4G08BABWP
PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2gb_nand_m29b__2.fm - Rev. I 1/06 EN
16
2004 Micron Technology, Inc. All rights reserved.
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
Bus Operation
The bus on the MT29Fxxx devices is multiplexed. Data I/O, addresses, and commands
all share the same pins. I/O pins I/O[15:8] are used only for data in the x16 configura-
tion. Addresses and commands are always supplied on I/O[7:0].
The command sequence normally consists of a command latch cycle, an ADDRESS
LATCH cycle, and a DATA cycle—either READ or WRITE.
Control Signals
CE#, WE#, RE#, CLE, ALE and WP# control Flash device READ and WRITE operations.
On the 8Gb MT29F8G08FAB, CE# and CE2# each control independent 4Gb arrays. CE2#
functions the same as CE# for its own array; all operations described for CE# also apply
to CE2#.
CE# is used to enable the device. When CE# is LOW and the device is not in the busy
state, the Flash memory will accept command, data, and address information.
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power con-
sumption. See Figure 40 on page 45 and Figure 47 on page 50 for examples of CE# “Don’t
Care” operations.
The CE# “Don’t Care” operation allows the NAND Flash to reside on the same asynchro-
nous memory bus as other Flash or SRAM devices. Other devices on the memory bus
can then be accessed while the NAND Flash is busy with internal operations. This capa-
bility is important for designs that require multiple NAND Flash devices on the same
bus. One device can be programmed while another is being read.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an address input cycle is occurring.
Commands
Commands are written to the command register on the rising edge of WE# when:
CE# and ALE are LOW, and
CLE is HIGH, and
The device is not busy
The exceptions to this are the READ STATUS and RESET commands. Commands are
transferred to the command register on the rising edge of WE#. See Figure 34 on page 42.
Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must
be written with zeros when issuing a command.
Address Input
Addresses are written to the address register on the rising edge of WE# when:
CE# and CLE are LOW, and
ALE is HIGH, and
The device is not busy
Addresses are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be
written with zeros when issuing an address.
Generally all five ADDRESS cycles are written to the device. An exception to this is the
BLOCK ERASE command, which requires only three ADDRESS cycles. See “BLOCK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT29F4G08BABWP-ET 功能描述:IC FLASH 4GBIT 48TSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤(pán) 其它名稱(chēng):Q2841869
MT29F4G08BABWP-ET TR 功能描述:IC FLASH 4GBIT 48TSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤(pán) 其它名稱(chēng):Q2841869
MT29F4G08BBBWP 功能描述:IC FLASH 4GBIT 48TSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤(pán) 其它名稱(chēng):Q2841869
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