參數(shù)資料
型號(hào)： MT29F4G08BABWP
元件分類(lèi)： PROM
英文描述： 512M X 8 FLASH 2.7V PROM, 18 ns, PDSO48
封裝： LEAD FREE, TSOP1-48
文件頁(yè)數(shù)： 9/57頁(yè)
文件大?。?/td> 1057K
代理商： MT29F4G08BABWP
PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2gb_nand_m29b__2.fm - Rev. I 1/06 EN
17
2004 Micron Technology, Inc. All rights reserved.
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
Bus Operation
RANDOM DATA INPUT and OUTPUT commands need only column addresses, so only
two ADDRESS cycles are required. Refer to the command descriptions to determine the
addressing requirements for each command.
Data Input
Data is written to the data register on the rising edge of WE# when:
CE#, CLE, and ALE are LOW, and
The device is not busy
Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure 36 on
page 43 for additional data input details.
READs
After a READ command is sent to the memory device, data is transferred from the mem-
ory array to the data register in tR. Typically tR is 25s. When data is available in the data
register, it is clocked out of the part by RE# going LOW. See Figure 39 on page 44 for
detailed timing information.
The READ STATUS (70h) command or the R/B# signal can be used to determine when
the device is ready. See the STATUS READ command section on page 27 for details.
Ready/Busy#
The R/B# output provides a hardware method of indicating the completion of a PRO-
GRAM/ERASE/READ operation. The signal is typically HIGH, and transitions to LOW
after the appropriate command is written to the device. The signal pin’s open-drain
driver enables multiple R/B# outputs to be OR-tied. The signal requires a pull-up resis-
tor for proper operation. The READ STATUS command can be used in place of R/B#.
Typically R/B# would be connected to an interrupt pin on the system controller. See
On the 8Gb MT29F8G08FAB, R/B# provides an indication for the 4Gb section enabled by
CE#, and R/B2# does the same for the 4Gb section enabled by CE2#. R/B# and R/B2# can
be tied together, or they can be used separately to provide independent indications for
each 4Gb section.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# pin. The actual value used for Rp (Rp = resistance of pull-up resistor)
depends on the system timing requirements. Large values of Rp cause R/B# to be
delayed significantly. At the 10- to 90-percent points on the R/B# waveform, rise time is
approximately two time constants (TC).
Figure 11:
Time Constants
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# pin and the total load capacitance.
Refer to Figure 13 on page 18, and Figure 14 on page 19, which depict approximate Rp
values using a circuit load of 100pF.
The minimum value for Rp is determined by the output drive capability of the R/B# sig-
nal, the output voltage swing, and VCC.
TC = R × C
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT29F4G08BABWP-ET 功能描述:IC FLASH 4GBIT 48TSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤(pán) 其它名稱(chēng):Q2841869
MT29F4G08BABWP-ET TR 功能描述:IC FLASH 4GBIT 48TSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤(pán) 其它名稱(chēng):Q2841869
MT29F4G08BBBWP 功能描述:IC FLASH 4GBIT 48TSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤(pán) 其它名稱(chēng):Q2841869
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