參數(shù)資料
型號: PERICOMPI7C8150
廠商: Pericom Semiconductor Corp.
英文描述: 2-Port PCI-to-PCI Bridge
中文描述: 2端口PCI至PCI橋
文件頁數(shù): 101/106頁
文件大小: 904K
代理商: PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
91
August 22, 2002 – Revision 1.02
17.3
AC SPECIFICATIONS
Figure 17-1. PCI Signal Timing Measurement Conditions
66 MHz
Min.
3
5
0
2
2
2
-
33 MHz
Symbol
Tsu
Tsu(ptp)
Th
Tval
Tval(ptp)
Ton
Toff
Parameter
Input setup time to CLK – bused signals
1,2,3
Input setup time to CLK – point-to-point
1,2,3
Input signal hold time from CLK
1,2
CLK to signal valid delay – bused signals
1,2,3
CLK to signal valid delay – point-to-point
1,2,3
Float to active delay
1,2
Active to float delay
1,2
Max.
-
-
-
6
6
-
14
Min.
7
10, 12
4
0
2
2
2
-
Max.
-
-
-
11
12
-
28
Units
ns
1. See Figure 17-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface
signals are synchronized to S_CLKOUT.
3. Point-to-point signals are P_REQ_L, S_REQ_L[7:0], P_GNT_L, S_GNT_L[7:0],
HSLED, HS_SW_L, HS_EN, and ENUM_L. Bused signals are P_AD, P_BDE_L, P_PAR,
P_PERR_L, P_SERR_L, P_FRAME_L, P_IRDY_L, P_TRDY_L, P_LOCK_L,
P_DEVSEL_L, P_STOP_L, P_IDSEL, S_AD, S_CBE_L, S_PAR, S_PERR_L,
S_SERR_L, S_FRAME_L, S_IRDY_L, S_TRDY_L, S_LOCK_L, S_DEVSEL_L, and
S_STOP_L.
4. REQ_L signals have a setup of 10 and GNT_L signals have a setup of 12.
17.4
66MHZ TIMING
Symbol
T
SKEW
T
DELAY
T
CYCLE
T
HIGH
T
LOW
Parameter
SKEW among S_CLKOUT[9:0]
DELAY between PCLK and S_CLKOUT[9:0]
PCLK, S_CLKOUT[9:0] cycle time
PCLK, S_CLKOUT[9:0] HIGH time
PCLK, S_CLKOUT[9:0] LOW time
Condition
Min.
0
4.6
15
6
6
Max.
0.250
5.5
30
Units
20pF load
ns
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