參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 35/106頁(yè)
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
25
August 22, 2002 – Revision 1.02
and the SERR_L enable bit (bit 8 of command register for secondary bus) are set,
PI7C8150 asserts P_SERR_L if the master-abort-on-posted-write is not set. The master-
abort-on-posted-write bit is bit 4 of the P_SERR_L event disable register (offset 64h).
Note:
When PI7C8150 performs a Type 1 to special cycle conversion, a master abort is the
expected termination for the special cycle on the target bus. In this case, the master abort
received bit is not set, and the Type 1 configuration transaction is disconnected after the
first data phase.
3.8.3
TARGET TERMINATION RECEIVED BY PI7C8150
When PI7C8150 initiates a transaction on the target bus and the target responds with
DEVSEL_L, the target can end the transaction with one of the following types
of termination:
Normal termination (upon de-assertion of FRAME_L)
Target retry
Target disconnect
Target abort
PI7C8150 handles these terminations in different ways, depending on the type of
transaction being performed.
3.8.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8150 initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 4–7 shows the response
to each type of target termination that occurs during a delayed write transaction.
PI7C8150 repeats a delayed write transaction until one of the following conditions is met:
PI7C8150 completes at least one data transfer.
PI7C8150 receives a master abort.
PI7C8150 receives a target abort.
PI7C8150 makes 2
24
(default) or 2
32
(maximum) write attempts resulting in a response of
target retry.
Table 4-7. Delayed Write Target Termination Response
Target Termination
Normal
Response
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
Target Retry
Target Disconnect
Target Abort
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