參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 61/106頁(yè)
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
51
August 22, 2002 – Revision 1.02
7.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C8150 ignores upstream lock and transactions. PI7C8150 will pass these transactions as
normal transactions without lock established.
7.3
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, PI7C8150 must
maintain the lock on the target bus for any subsequent locked transactions until the initiator
relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a
locked sequence. On subsequent transactions in the sequence,
the target retry has no effect on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock. PI7C8150
does not know whether the current transaction is the last one in a sequence of locked
transactions until the initiator de-asserts the LOCK_L signal at
end of the transaction.
When the last locked transaction is a delayed transaction, PI7C8150 has already completed
the transaction on the target bus. In this example, as soon as PI7C8150 detects that the
initiator has relinquished the LOCK_L signal by sampling it in the de-asserted state while
FRAME_L is de-asserted, PI7C8150 de-asserts the LOCK_L signal on the target bus as
soon as possible. Because of this behavior, LOCK_L may not be de-asserted until several
cycles after the last locked transaction has been completed on the target bus. As soon as
PI7C8150 has de-asserted LOCK_L to indicate the end of a sequence of locked
transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C8150 de-asserts
LOCK_L on the target bus at the end of the transaction because the lock was relinquished
at the end of the write transaction on the initiator bus.
When PI7C8150 receives a target abort or a master abort in response to a locked delayed
transaction, PI7C8150 returns a target abort or a master abort when the initiator repeats the
locked transaction. The initiator must then de-assert LOCK_L at the end of the transaction.
PI7C8150 sets the appropriate status bits, flagging the abnormal target termination
condition (see Section 4.8). Normal forwarding of unlocked posted and delayed
transactions is resumed.
When PI7C8150 receives a target abort or a master abort in response to a locked posted
write transaction, PI7C8150 cannot pass back that status to the initiator. PI7C8150 asserts
SERR_L on the initiator bus when a target abort or a master abort is received during a
locked posted write transaction, if the SERR_L enable bit is set in the command register.
Signal SERR_L is asserted for the master abort condition if the master abort mode bit is set
in the bridge control register (see Section 7.4).
8
PCI BUS ARBITRATION
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