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參數(shù)資料
| 型號(hào)： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁(yè)數(shù)： | 82/106頁(yè) |
| 文件大小： | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
72
August 22, 2002 – Revision 1.02
Bit
0
1
Function
Reserved
Memory Write
Disconnect
Control
Type
R/O
R/W
Description
Reserved. Returns 0 when read. Reset to 0
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls whether the bridge supports memory read flow-through
3:2
4
Reserved
Memory Read
Flow-Through
Control
R/O
R/W
0: Enable
1: Disable
Reset to 0
Enables hardware control of transaction forwarding.
5
Live Insertion
Mode
R/W
0: GPIO[3] has no effect on the I/O, memory, and master enable bits
1: If GPIO[3] is set to input mode, this bit enables GPIO[3] to mask
I/O enable, memory enable and master enable bits to 0. PI7C8150
will stop accepting I/O and memory transactions as a result.
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls the chip and secondary bus reset.
7:6
8
Reserved
Chip Reset
R/O
R/WR
0: PI7C8150 is ready for operation
1: Causes PI7C8150 to perform a chip reset
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
10:9
Test Mode For
All Counters at P
and S1
R/O
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
15:11
Reserved
R/O
14.1.30
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
24:16
Function
Arbiter Control
Type
R/W
Description
Each bit controls whether a secondary bus master is assigned to the
high priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ[8:0]
0: low priority
1: high priority
Reset to 0
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