參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 92/106頁(yè)
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
82
August 22, 2002 – Revision 1.02
well as monitoring the P_DEVSEL_L for
other fast and medium devices on the
Primary Port.
PI7C8150 asserts P_DEVSEL_L,
terminates the cycle normally if it is able
to be posted, otherwise return with a retry.
It then passes the cycle to the appropriate
port. When the cycle is complete on the
target port, it will wait for the initiator to
repeat the same cycle and end with normal
termination.
PI7C8150 does not respond and the cycle
will terminate as master abort.
PI7C8150 does not respond.
Master on Primary
Target on Secondary
Master on Primary
Target not on Primary nor
Secondary Port
Target on the same
Secondary Port
Target on Primary or the
other Secondary Port
Master on Secondary
Master on Secondary
PI7C8150 asserts S_DEVSEL_L,
terminates the cycle normally if it is able
to be posted, otherwise returns with a
retry. It then passes the cycle to the
appropriate port. When cycle is complete
on the target port, it will wait for the
initiator to repeat the same cycle and end
with normal termination.
PI7C8150 does not respond.
Master on Secondary
Target not on Primary nor
the other Secondary Port
15.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
15.2.1
MASTER ABORT
Master abort indicates that when PI7C8150 acts as a master and receives no response (i.e.,
no target asserts DEVSEL_L or S_DEVSEL_L) from
a target, the bridge de-asserts FRAME_L and then de-asserts IRDY_L.
15.2.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,
and S_PAR signals. Parity should be even (i. e. an even number of‘1’s) across AD, CBE,
and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For
reads, even parity must be generated using the initiators CBE signals combined with the
read data. Again, the PAR signal corresponds to read data from the previous data phase
cycle.
15.2.3
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the
P_SERR_L signal by asserting P_SERR_L for one cycle and then 3-stating two cycles
after the bad address. P_SERR_L can only be asserted if bit 6 and 8 in the Command
Register are both set to 1. For write data phases, a parity error should be reported by
asserting the P_PERR_L signal two cycles after the data phase and should remain asserted
for one cycle when bit 6 in the Command register is set to a 1.
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