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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 74/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
64
August 22, 2002 – Revision 1.02
2
Bus Master
Enable
R/W
Controls ability to operate as a bus master on the primary interface
0: do not initiate memory or I/O transactions on the primary
interface and disable response to memory and I/O transactions on
the secondary interface
1: enables 7C8150 to operate as a master on the primary interfaces
for memory and I/O transactions forwarded from the secondary
interface
Reset to 0
No special cycles defined.
Bit is defined as read only and returns 0 when read
Memory write and invalidate not supported.
Bit is implemented as read only and returns 0 when read (unless
forwarding a transaction for another master)
Controls response to VGA compatible palette accesses
3
Special Cycle
Enable
Memory Write
And Invalidate
Enable
R/O
4
R/O
5
VGA Palette
Snoop Enable
R/W
0: ignore VGA palette accesses on the primary
1: enable positive decoding response to VGA palette writes on the
primary interface with I/O address bits AD[9:0] equal to 3C6h,
3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded
and may be any value)
Controls response to parity errors
6
Parity Error
Response
R/W
0: 7C8150 may ignore any parity errors that it detects and continue
normal operation
1: 7C8150 must take its normal action when a parity error is
detected
Reset to 0
Controls the ability to perform address / data stepping
7
Wait Cycle
Control
R/O
0: disable address/data stepping (affects primary and secondary)
1: enable address/data stepping (affects primary and secondary)
Reset to 0
Controls the enable for the P_SERR_L pin
8
P_SERR_L
enable
R/W
0: disable the P_SERR_L driver
1: enable the P_SERR_L driver
Reset to 0
Controls 7C8150’s ability to generate fast back-to-back transactions
to different devices on the primary interface.
9
Fast Back-to-
Back Enable
R/W
0: no fast back-to-back transactions
1: enable fast back-to-back transactions
Reset to 0
Returns 000000 when read
15:10
Reserved
R/O
14.1.4
STATUS REGISTER – OFFSET 04h
Bit
19:16
Function
Reserved
Type
R/O
Description
Reset to 0
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