參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 31/106頁(yè)
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
21
August 22, 2002 – Revision 1.02
Leaves unchanged the function number and register number fields.
PI7C8150 asserts a unique address line based on the device number. These address lines
may be used as secondary bus IDSEL signals. The mapping of the address lines depends on
the device number in the Type 1 address bits P_AD[15:11]. Table 4–6 presents the
mapping that PI7C8150 uses.
Table 4-6. Device Number to IDSEL S_AD Pin Mapping
Device Number
P_AD[15:11]
0h
00000
1h
00001
2h
00010
3h
00011
4h
00100
5h
00101
6h
00110
7h
00111
8h
01000
9h
01001
Ah
01010
Bh
01011
Ch
01100
Dh
01101
Eh
01110
Fh
01111
10h – 1Eh
10000 – 11110
1Fh
11111
Secondary IDSEL S_AD[31:16]
0000 0000 0000 0001
0000 0000 0000 0010
0000 0000 0000 0100
0000 0000 0000 1000
0000 0000 0001 0000
0000 0000 0010 0000
0000 0000 0100 0000
0000 0000 1000 0000
0000 0001 0000 0000
0000 0010 0000 0000
0000 0100 0000 0000
0000 1000 0000 0000
0001 0000 0000 0000
0010 0000 0000 0000
0100 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
Generate special cycle (P_AD[7:2] = 00h)
0000 0000 0000 0000 (P_AD[7:2] = 00h)
S_AD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
-
PI7C8150 can assert up to 9 unique address lines to be used as IDSEL signals for
up to 9 devices on the secondary bus, for device numbers ranging from 0 through 8.
Because of electrical loading constraints of the PCI bus, more than 9 IDSEL signals should
not be necessary. However, if device numbers greater than 9 are desired, some external
method of generating IDSEL lines must be used, and no upper address bits are then
asserted. The configuration transaction is still translated and passed from the primary bus to
the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends
in a master abort.
PI7C8150 forwards Type 1 to Type 0 configuration read or write transactions as delayed
transactions. Type 1 to Type 0 configuration read or write transactions are limited to a
single 32-bit data transfer.
3.7.3
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism
when two or more levels of PCI-to-PCI bridges are used.
When PI7C8150 detects a Type 1 configuration transaction intended for a PCI bus
downstream from the secondary bus, PI7C8150 forwards the transaction unchanged to the
secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command
or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1
to Type 1 forwarding occurs when the following conditions are met during the address
phase:
The lowest two address bits are equal to 01b.
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