參數(shù)資料
型號(hào): PERICOMPI7C8150
廠商: Pericom Semiconductor Corp.
英文描述: 2-Port PCI-to-PCI Bridge
中文描述: 2端口PCI至PCI橋
文件頁(yè)數(shù): 70/106頁(yè)
文件大?。?/td> 904K
代理商: PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
60
August 22, 2002 – Revision 1.02
When S_RESET_L is asserted by means of the secondary reset bit, PI7C8150 remains
accessible during secondary interface reset and continues to respond to accesses to its
configuration space from the primary interface.
12.3
CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the PI7C8150 and
the secondary bus.
When the chip reset bit is set, all registers and chip state are reset and all signals are
tristated. S_RESET_L is asserted and the secondary reset bit is automatically set.
S_RESET_L remains asserted until a configuration write operation clears the secondary
reset bit and the serial clock mask has been shifted in. Within 20 PCI clock cycles after
completion of the configuration write operation, PI7C8150’s reset bit automatically clears
and PI7C8150 is ready for configuration.
During reset, PI7C8150 is inaccessible.
13
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
13.1
PRIMARY INTERFACE
P_CBE [3:0]
0000
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
Action
Ignore
0001
0010
Do not claim. Ignore.
1. If address is within pass through I/O range, claim and pass
through.
2. Otherwise, do not pass through and do not claim for
internal access.
Same as I/O Read.
-----
-----
1. If address is within pass through memory range, claim and
pass through.
0011
0100
0101
0110
I/O Write
Reserved
Reserved
Memory Read
2. If address is within pass through memory mapped I/O
range, claim and pass through.
3. Otherwise, do not pass through and do not claim for
internal access.
Same as Memory Read.
-----
-----
Type 0 Configuration Read:
If the bridge’s IDSEL line is asserted, perform function
decode and claim if target function is implemented.
Otherwise, ignore. If claimed, permit access to target
function’s configuration registers. Do not pass through
under any circumstances.
0111
1000
1001
1010
Memory Write
Reserved
Reserved
Configuration Read
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