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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 52/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
42
August 22, 2002 – Revision 1.02
When parity error is forwarded back from the target bus
For downstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150 has write status to return, the following events occur:
PI7C8150 first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if the
primary interface parity-error-response bit is set in the command register.
PI7C8150 sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150 has write status to return, the following events occur:
PI7C8150 first asserts S_TRDY_L and then asserts S_PERR_L two cycles later, if the
secondary interface parity-error-response bit is set in the bridge control register (offset
3Ch).
PI7C8150 sets the secondary interface parity-error-detected bit in the secondary status
register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
PI7C8150 asserts P_PERR_L two cycles after the data transfer, if the following are
both true:
The parity-error-response bit is set in the command register of the primary
interface.
The parity-error-response bit is set in the bridge control register of the
secondary interface.
PI7C8150 completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
PI7C8150 asserts S_PERR_L two cycles after the data transfer, if the following are
both true:
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the
secondary interface.
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