參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠(chǎng)商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 56/106頁(yè)
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
46
August 22, 2002 – Revision 1.02
Table 7–4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
The PI7C8150 must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR_L signal is detected asserted or a parity error is detected on the
secondary bus.
Table 7-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Secondary
Detected
Parity
Detected Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
0
1
0
0
0
1
0
0
0
1
0
0
X= don’t care
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Table 7–5 shows assertion of P_PERR_L. This signal is set under the following conditions:
PI7C8150 is either the target of a write transaction or the initiator of a read transaction
on the primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8150 detects a data parity error on the primary bus or detects S_PERR_L asserted
during the completion phase of a downstream delayed write transaction on the target
(secondary) bus.
Table 7-5. Assertion of P_PERR#
P_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 / 1
x / x
x / x
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
0
2
1
1
X
= don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
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