參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 23/106頁
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
13
August 22, 2002 – Revision 1.02
The posted write data buffer fills up.
When one of the last two events occurs, the PI7C8150 returns a target disconnect to the
requesting initiator on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C8150 asserts
its request on the target bus. This can occur while PI7C8150 is still receiving data on the
initiator bus. When the grant for the target bus is received and the target bus is detected in
the idle condition, PI7C8150 asserts FRAME_L and drives the stored write address out on
the target bus. On the following cycle, PI7C8150 drives the first DWORD of write data and
continues to transfer write data until all write data corresponding to that transaction is
delivered, or until a target termination is received.
As long as write data exists in the queue, PI7C8150 can drive one DWORD of write data
each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing
through PI7C8150 and the initiator stalls, PI7C8150 will signal the last data phase for the
current transaction at the target bus if the queue empties. PI7C8150 will restart the follow-
on transactions if the queue has new data.
PI7C8150 ends the transaction on the target bus when one of the following conditions is
met:
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C8150 starts another
transaction to deliver the rest of the write data).
The target returns a target abort (PI7C8150 discards remaining write data).
The master latency timer expires, and PI7C8150 no longer has the target bus grant
(PI7C8150 starts another transaction to deliver remaining write data).
Section 4.8.3.2 provides detailed information about how PI7C8150 responds to target
termination during posted write transactions.
3.5.2
MEMORY WRITE AND INVALIDATE
Posted write forwarding is used for Memory Write and Invalidate transactions.
The PI7C8150 disconnects Memory Write and Invalidate commands at aligned cache line
boundaries. The cache line size value in the cache line size register gives the number of
DWORD in a cache line.
If the value in the cache line size register does meet the memory write and invalidate
conditions, the PI7C8150 returns a target disconnect to the initiator on a cache line
boundary.
3.5.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write
transactions.
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