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參數(shù)資料
| 型號(hào)： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁(yè)數(shù)： | 75/106頁(yè) |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
65
August 22, 2002 – Revision 1.02
20
Capabilities List
R/O
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1
Set to 1 to enable 66MHz operation on the primary interface
21
66MHz Capable
R/O
Reset to 1
Reset to 0
Set to 1 to enable decoding of fast back-to-back transactions on the
primary interface to different targets
22
23
Reserved
Fast Back-to-
Back Capable
R/O
R/O
Reset to 1
Set to 1 when P_PERR_L is asserted and bit 6 of command register
is set
24
Data Parity Error
Detected
R/WC
Reset to 0
DEVSEL_L timing (medium decoding)
26:25
DEVSEL_L
timing
R/O
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs
27
Signaled Target
Abort
R/WC
Reset to 0
Set to 1 (by a master device) whenever transactions are terminated
with target aborts
28
Received Target
Abort
R/WC
Reset to 0
Set to 1 (by a master) when transactions are terminated with Master
Abort
29
Received Master
Abort
R/WC
Reset to 0
Set to 1 when P_SERR_L is asserted
30
Signaled System
Error
R/WC
Reset to 0
Set to 1 when address or data parity error is detected on the primary
interface
31
Detected Parity
Error
R/WC
Reset to 0
14.1.5
REVISION ID REGISTER – OFFSET 08h
Bit
7:0
Function
Revision
Type
R/O
Description
Indicates revision number of device. Hardwired to 01h
14.1.6
CLASS CODE REGISTER – OFFSET 08h
Bit
15:8
Function
Programming
Interface
Sub-Class Code
Base Class Code
Type
R/O
Description
Read as 0 to indicate no programming interfaces have been defined
for PCI-to-PCI bridges
Read as 04h to indicate device is PCI-to-PCI bridge
Read as 06h to indicate device is a bridge device
23:16
31:24
R/O
R/O
14.1.7
CACHE LINE SIZE REGISTER – OFFSET 0Ch
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