參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 58/106頁(yè)
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
48
August 22, 2002 – Revision 1.02
1
1
1
1
X
= don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary)
bus.
3
The parity error was detected on the target (primary) bus but not on the initiator (secondary)
bus.
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
x / x
x / x
x / x
x / x
6.4
SYSTEM ERROR (SERR#) REPORTING
PI7C8150 uses the P_SERR_L signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section 7.2.3.
Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the
following conditions apply:
For PI7C8150 to assert P_SERR_L for any reason, the SERR_L enable bit must be set
in the command register.
Whenever PI7C8150 asserts P_SERR_L, PI7C8150 must also set the signaled system
error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150 asserts
P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the
SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150 also
sets the received system error bit in the secondary status register.
PI7C8150 also conditionally asserts P_SERR_L for any of the following reasons:
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
24
(default) attempts to deliver (2
24
target retries
received)
Parity error reported on target bus during posted write transaction (see previous
section)
Delayed write data discarded after 2
24
(default) attempts to deliver (2
24
target retries
received)
Delayed read data cannot be transferred from target after 2
24
(default) attempts (2
24
target retries received)
Master timeout on delayed transaction
The device-specific P_SERR_L status register reports the reason for the assertion of
P_SERR_L. Most of these events have additional device-specific disable bits in the
P_SERR_L event disable register that make it possible to mask out P_SERR_L assertion
相關(guān)PDF資料
PDF描述
PESDXL2BT Low capacitance double bidirectional ESD protection diodes in SOT23
PESDXL2UM LJT 23C 21#20 2#16 PIN RECP
PETAM1270BK300R BRAID SLEEVING 300M
PETAM1270BK50C 5V RS232 Transceiver with One Receiver Active in SHUTDOWN
PETAM1901BK200R BRAID SLEEVING 300M
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PERINCSPRT5PKM 制造商:Dialogic Corporation 功能描述:SERVICE;5PK;PERINCIDENT;HW;SUP
PER-M18 制造商:AAEON 制造商全稱(chēng):AAEON 功能描述:Desktop Stand For ONYX-150/ 153/ 154/ 172/ 192/ 1722/ 1922/ 2122/ 2215 (VESA 100)
PER-M20 制造商:AAEON 制造商全稱(chēng):AAEON 功能描述:Desktop Stand For ONYX-170/ 172/ 173/ 174/ 175/ 175S/175X/ 175V/ 190/ 192/ 193/ 195/ 195S/ 195X/195V/ 1722/ 1922/ 2122/ 2217/ 2219 (VESA 100/75)
PERMARK-FB-1/2-1.50-9 制造商:TE Connectivity 功能描述:PERMARK-FB-1/2-1.50-9
PERMARK-FB-1/2-NO.21-9 制造商:TE Connectivity 功能描述:PERMARK-FB-1/2-NO.21-9
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*