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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 27/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
17
August 22, 2002 – Revision 1.02
Type of Transaction
Address Space
Cache
(CLS)
*
*
*
CLS = 0 or 16
Line
Size
Prefetch
Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address
boundary
Cache line address boundary
16-DWORD aligned address
boundary
Cache line boundary
32-DWORD aligned address
boundary
2X of cache line boundary
Aligned
Address
Configuration Read
I/O Read
Memory Read
Memory Read
-
-
Non-Prefetchable
Prefetchable
Memory Read
Memory Read Line
Prefetchable
-
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
Memory Read Line
Memory Read Multiple
-
-
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
Memory Read Multiple
- does not matter if it is prefetchable or non-prefetchable
* don’t care
-
CLS = 1, 2, 4, 8, 16
Table 4-5. Read Transaction Prefetching
Type of Transaction
I/O Read
Configuration Read
Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Prefetching always used
Memory Read
Memory Read Line
Memory Read Multiple
See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces.
3.6.4
DELAYED READ REQUESTS
PI7C8150 treats all read transactions as delayed read transactions, which means
that the read request from the initiator is posted into a delayed transaction queue.
Read data from the target is placed in the read data queue directed toward the initiator bus
interface and is transferred to the initiator when the initiator repeats
the read transaction.
When PI7C8150 accepts a delayed read request, it first samples the read address, read bus
command, and address parity. When IRDY_L is asserted, PI7C8150 then samples the byte
enable bits for the first data phase. This information is entered into the delayed transaction
queue. PI7C8150 terminates the transaction by signaling a target retry to the initiator. Upon
reception of the target retry, the initiator is required to continue to repeat the same read
transaction until at least one data transfer is completed, or until a target response (target
abort or master abort) other than a target retry is received.
3.6.5
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches the head of the delayed transaction queue, PI7C8150
arbitrates for the target bus and initiates the read transaction only if all previously queued
posted write transactions have been delivered. PI7C8150 uses the exact read address and
read command captured from the initiator during the initial delayed read request to initiate
the read transaction. If the read transaction is a non-prefetchable read, PI7C8150 drives the
captured byte enable bits during the next cycle. If the transaction is a prefetchable read
transaction, it drives all byte enable bits to zero for all data phases. If PI7C8150 receives a
target retry in response to the read transaction on the target bus, it continues to repeat the
read transaction until at least one data transfer is completed, or until an error condition is
encountered. If the transaction is terminated via normal master termination or target
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