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參數資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數： | 5/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
v
August 22, 2002 – Revision 1.02
4.3
MEMORY ADDRESS DECODING ........................................................................................... 31
4.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
......................... 32
4.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS
................. 33
4.4
VGA SUPPORT........................................................................................................................... 34
4.4.1
VGA MODE
......................................................................................................................... 34
4.4.2
VGA SNOOP MODE
........................................................................................................... 34
5
TRANSACTION ORDERING.......................................................................................................... 35
5.1
5.2
5.3
5.4
TRANSACTIONS GOVERNED BY ORDERING RULES ....................................................... 35
GENERAL ORDERING GUIDELINES ..................................................................................... 36
ORDERING RULES.................................................................................................................... 36
DATA SYNCHRONIZATION.................................................................................................... 37
6
ERROR HANDLING......................................................................................................................... 38
6.1
6.2
ADDRESS PARITY ERRORS.................................................................................................... 38
DATA PARITY ERRORS........................................................................................................... 39
6.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE
.......... 39
6.2.2
READ TRANSACTIONS
.................................................................................................... 39
6.2.3
DELAYED WRITE TRANSACTIONS
............................................................................... 40
6.2.4
POSTED WRITE TRANSACTIONS
.................................................................................. 43
6.3
DATA PARITY ERROR REPORTING SUMMARY................................................................. 44
6.4
SYSTEM ERROR (SERR#) REPORTING................................................................................. 48
7
EXCLUSIVE ACCESS...................................................................................................................... 49
7.1
7.2
CONCURRENT LOCKS............................................................................................................. 49
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150....................................................... 49
7.2.1
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION
..................................... 49
7.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
.............................................. 51
7.3
ENDING EXCLUSIVE ACCESS................................................................................................ 51
8
PCI BUS ARBITRATION................................................................................................................. 51
8.1
8.2
PRIMARY PCI BUS ARBITRATION........................................................................................ 52
SECONDARY PCI BUS ARBITRATION.................................................................................. 52
8.2.1
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER
.................... 52
8.2.2
PREEMPTION
.................................................................................................................... 54
8.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER
...................... 54
8.2.4
BUS PARKING
.................................................................................................................... 54
9
CLOCKS............................................................................................................................................. 55
9.1
9.2
PRIMARY CLOCK INPUTS....................................................................................................... 55
SECONDARY CLOCK OUTPUTS ............................................................................................ 55
10
GENERAL PURPOSE I/O INTERFACE.................................................................................... 55
10.1
10.2
10.3
GPIO CONTROL REGISTERS................................................................................................... 55
SECONDARY CLOCK CONTROL............................................................................................ 56
LIVE INSERTION....................................................................................................................... 58
11
PCI POWER MANAGEMENT.................................................................................................... 58
12
RESET............................................................................................................................................. 59
12.1
12.2
12.3
PRIMARY INTERFACE RESET................................................................................................ 59
SECONDARY INTERFACE RESET.......................................................................................... 59
CHIP RESET................................................................................................................................ 60
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