參數資料
型號： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數： 55/106頁
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
45
August 22, 2002 – Revision 1.02
0
1
0
0
0
X
= don’t care
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Upstream
Downstream
Downstream
Upstream
Upstream
Secondary
Primary
Secondary
Primary
Secondary
x / x
x / x
x / x
x / x
x / x
Table 7–2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8150 detects a parity
error on the secondary interface.
Table 7-2. Setting Secondary Interface Detected Parity Error Bit
Secondary
Detected
Parity
Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
0
1
0
0
0
0
0
1
0
0
0
1
X
= don’t care
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Table 7–3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
PI7C8150 must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
Table 7-3. Setting Primary Interface Master Data Parity Error Detected Bit
Primary
Data
Parity Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
0
0
1
0
0
0
1
0
0
0
1
0
X
= don’t care
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
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