參數(shù)資料
型號： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 8/106頁
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
viii
August 22, 2002 – Revision 1.02
Table 4-5. Read Transaction Prefetching
_________________________________________________ 17
Table 4-6. Device Number to IDSEL S_AD Pin Mapping
____________________________________ 21
Table 4-7. Delayed Write Target Termination Response
_____________________________________ 25
Table 4-8. Response to Posted Write Target Termination
____________________________________ 26
Table 4-9. Response to Delayed Read Target Termination
___________________________________ 27
Table 6-1. Summary of Transaction Ordering
_____________________________________________ 36
Table 7-1. Setting the Primary Interface Detected Parity Error Bit
____________________________ 44
Table 7-2. Setting Secondary Interface Detected Parity Error Bit
______________________________ 45
Table 7-3. Setting Primary Interface Master Data Parity Error Detected Bit
_____________________ 45
Table 7-4. Setting Secondary Interface Master Data Parity Error Detected Bit
___________________ 46
Table 7-5. Assertion of P_PERR#
_______________________________________________________ 46
Table 7-6. Assertion of S_PERR#
_______________________________________________________ 47
Table 7-7. Assertion of P_SERR# for Data Parity Errors
____________________________________ 47
Table 11-1. GPIO Operation
___________________________________________________________ 56
Table 11-2. GPIO Serial Data Format
___________________________________________________ 57
Table 12-1. Power management transitions
_______________________________________________ 58
Table 16-1. TAP Pins
_________________________________________________________________ 85
Table 16-2. JTAG Boundary Register Order
_______________________________________________ 86
LIST OF FIGURES
Figure 9-1. Secondary Arbiter Example
...................................................................................................... 53
Figure 16-1. Test Access Port Block Diagram
............................................................................................ 84
Figure 17-1. PCI Signal Timing Measurement Conditions
......................................................................... 91
Figure 18-1. 208-pin FQFP Package Outline
............................................................................................... 92
Figure 18-2. 256-ball PBGA Package Outline
............................................................................................. 93
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