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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 68/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
58
August 22, 2002 – Revision 1.02
10.3
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
To enable live insertion mode, the live insertion mode bit in the chip control register must
be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO
output enable control register. When live insertion mode is enabled, whenever GPIO[3] is
driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are
internally masked to 0. This means that, as a target, PI7C8150 no longer accepts any I/O or
memory transactions, on either interface. When read, the register bits still reflect the value
originally written by a configuration write command; when GPIO[3] is deasserted, the
internal enable bits return to their original value (as they appear when read from the
command register). When this mode is enabled, as a master, PI7C8150 completes any
posted write or delayed request transactions that have already been queued.
Delayed completion transactions are not returned to the master in this mode because
PI7C8150 is not responding to any I/O or memory transactions during this time. PI7C8150
continues to accept configuration transactions in live insertion mode. Once live insertion
mode brings PI7C8150 to a halt and queued transactions are completed, the secondary reset
bit in the bridge control register can be used to assert S_RST_L, if desired, to reset and tri-
state secondary bus devices, and to enable any live insertion hardware.
11
PCI POWER MANAGEMENT
PI7C8150
incorporates functionality that meets the requirements of the
PCI Power
Management Specificatio
n,
Revision 1.
0. These features include:
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
Support for D0, D3
hot
and D3
cold
power management states
Support for D0, D1, D2, D3
hot
, and D3
cold
power management states for devices
behind the bridge
Support of the B2 secondary bus power state when in the D3
hot
power management
state
Table 12-1
shows the states and related actions that PI7C8150 performs during power
management transitions. (No other transactions are permitted.)
Table 12-1. Power management transitions
Current Status
D0
Next State
D3cold
Action
Power has been removed from PI7C8150. A power-up reset must be
performed to bring PI7C8150 to D0.
If enabled to do so by the BPCCE pin, PI7C8150 will disable the
secondary clocks and drive them LOW.
Unimplemented power state. PI7C8150 will ignore the write to the
power state bits (power state remains at D0).
Unimplemented power state. PI7C8150 will ignore the write to the
power state bits (power state remains at D0).
PI7C8150 enables secondary clock outputs and performs an internal
D0
D3hot
D0
D2
D0
D1
D3hot
D0
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