參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 88/106頁(yè)
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
78
August 22, 2002 – Revision 1.02
2
Primary MEMW
Command Alias
Enable
R/W
Controls PI7C8150’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
Controls PI7C8150’s detection mechanism for matching memory
read retry cycles from the initiator on the secondary
3
Secondary
MEMR
Command Alias
Enable
R/W
0: exact matching for memory read retry cycles from initiator on the
secondary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the secondary interface
Reset to 0
Controls PI7C8150’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
4
Secondary
MEMW
Command Alias
Enable
R/W
0: exact matching for non-posted memory write retry cycles from
initiator on the secondary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the secondary interface
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150’s ability to enable long requests for lock cycles
8:5
Reserved
R/O
9
Enable Long
Request
R/W
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
Control’s PI7C8150’s ability to enable the secondary bus to hold
requests longer.
10
Enable
Secondary To
Hold Request
Longer
R/W
0: internal secondary master will release REQ_L after FRAME_L
assertion
1: internal secondary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Control’s PI7C8150’s ability to hold requests longer at the Primary
Port.
11
Enable Primary
To Hold Request
Longer
R/W
0: internal Primary master will release REQ_L after FRAME_L
assertion
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Reserved. Returns 0 when read. Reset to 0.
15:12
Reserved
R/O
14.1.43
RETRY COUNTER REGISTER – OFFSET 78h
Bit
Function
Type
Description
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