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參數(shù)資料
| 型號： | PERICOMPI7C8150 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-Port PCI-to-PCI Bridge |
| 中文描述： | 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 69/106頁 |
| 文件大?。?/td> | 904K |
| 代理商： | PERICOMPI7C8150 |
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PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
59
August 22, 2002 – Revision 1.02
chip reset. Signal S_RST_L will not be asserted. All registers will
be returned to the reset values and buffers will be cleared.
Power has been removed from PI7C8150. A power-up reset must be
performed to bring PI7C8150 to D0.
Power-up reset. PI7C8150 performs the standard power-up reset
functions as described in Section 13.
D3hot
D3cold
D3cold
D0
PME# signals are routed from downstream devices around
PCI-to-PCI bridges. PME#
signals do not pass through PCI-to-PCI bridges.
12
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
12.1
PRIMARY INTERFACE RESET
PI7C8150 has a reset input, P_RESET_L. When P_RESET_L is asserted, the following
events occur:
PI7C8150 immediately 3-states all primary and secondary PCI interface signals.
PI7C8150 performs a chip reset.
Registers that have default values are reset.
P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLKOUT. PI7C8150 is not accessible during P_RESET_L. After P_RESET_L is de-
asserted, PI7C8150 remains inaccessible for 16 PCI clocks before the first configuration
transaction can be accepted.
12.2
SECONDARY INTERFACE RESET
PI7C8150 is responsible for driving the secondary bus reset signals, S_RESET_L.
PI7C8150 asserts S_RESET_L when any of the following conditions are met:
Signal P_RESET_L is asserted.
Signal S_RESET_L remains asserted as long as
P_RESET_L is asserted and does not de-assert until P_RESET_L is de-asserted.
The secondary reset bit in the bridge control register is set.
Signal S_RESET_L
remains asserted until a configuration write operation clears the secondary reset bit.
S_RESET_L pin is asserted.
When S_RESET_L is asserted, PI7C8150 immediately 3-
states all the secondary PCI interface signals associated with the secondary port. The
S_RESET_L in asserting and de-asserting edges can be asynchronous to P_CLK.
When S_RESET_L is asserted, all secondary PCI interface control signals, including the
secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S_PAR
are driven low for the duration of S_RESET_L assertion. All posted write and delayed
transaction data buffers are reset. Therefore, any transactions residing inside the buffers at
the time of secondary reset are discarded.
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