參數(shù)資料
型號： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 54/106頁
文件大小： 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
44
August 22, 2002 – Revision 1.02
PI7C8150 has not detected the parity error on the primary (initiator) bus
which the parity error is not forwarded from the primary bus to the
secondary bus.
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR_L, the following events occur:
PI7C8150 sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
PI7C8150 asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C8150 has not detected the parity error on the secondary (initiator) bus,
which the parity error is not forwarded from the secondary bus to the
primary bus.
Assertion of P_SERR_L is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator.
If the parity error has forwarded from the initiating bus to the target bus, P_SERR_L will
not be asserted.
6.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C8150 to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C8150 to data parity errors according to the status bits that PI7C8150 sets and the
signals that it asserts.
Table 7–1 shows setting the detected parity error bit in the status register, corresponding to
the primary interface. This bit is set when PI7C8150 detects a parity error on the primary
interface.
Table 7-1. Setting the Primary Interface Detected Parity Error Bit
Primary Detected
Parity Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
x / x
x / x
0
0
1
0
1
0
0
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
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