參數(shù)資料
型號： QADCRM
英文描述： Queued Analog-to-Digital Converter Reference Manual
中文描述： 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊
文件頁數(shù)： 103/122頁
文件大?。?/td> 940K
代理商： QADCRM
QADC
REFERENCE MANUAL
REGISTER SUMMARY
MOTOROLA
B-3
B.2.4 Port A/B Data Register
QADC ports A and B are accessed through two 8-bit port data registers (PORTQA and
PORTQB).
Port A pins are referred to as PQA[7:0] when used as a bidirectional 8-bit input/output
port that may be used for general-purpose digital input signals or digital open drain out-
put signals. Port A can also be used for analog inputs (AN[59:52]), external trigger in-
puts (ETRIG[2:1]), and external multiplexer address outputs (MA[2:0]).
Port B pins are referred to as PQB[7:0] when used as an input only 8-bit digital port
that may be used for general-purpose digital input signals. Port B can also be used for
nonmultiplexed (AN[51:48])/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog
inputs. Read operations on the reserved bits return zeros, and writes have no effect.
B.2.5 Port Data Direction Register
The port data direction register (DDRQA) is associated with the port A digital I/O pins.
The bidirectional pins have somewhat higher leakage and capacitance specifications.
Refer to
APPENDIX A ELECTRICAL CHARACTERISTICS
for more information. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in
this register cleared to zero configures the corresponding pin as an input. The software
is responsible for ensuring that DDR bits are not set to one on pins used for analog
inputs. When the DDR bit is set to one and the pin is selected for analog conversion,
the voltage sampled is that of the output digital driver as influenced by the load.
NOTE
Caution should be exercised when mixing digital and analog inputs.
This should be isolated as much as possible. Rise and fall times
should be as large as possible.
PORTQA — Port A Data Register
PORTQB — Port B Data Register
$####06
$####07
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PQA7
PQA6
PQA5
PQA4
PQA3
PQA2
PQA1
PQA0
PQB7
PQB6
PQB5
PQB4
PQB3
PQB2
PQB1
PQB0
RESET:
U
ANALOG CHANNEL:
AN59
AN58
EXTERNAL TRIGGER INPUTS:
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
AN57
AN56
AN55
AN54
AN53
AN52
AN51
AN50
AN49
AN48
AN3
AN2
AN1
AN0
ETRIG2 ETRIG1
MULTIPLEXED ADDRESS OUTPUTS:
MA2
MA1
MA0
MULTIPLEXED ANALOG INPUTS:
ANz
ANy
ANx
ANw
DDRQA —
Port Data Direction Register
$####08
15
14
13
12
11
10
9
8
7
6
5
4
RESERVED
3
2
1
0
DDQA7 DDQA6 DDQA5 DDQA4 DDQA3 DDQA2 DDQA1 DDQA0
RESET:
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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