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參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 57/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
DIGITAL CONTROL
MOTOROLA
7-11
To accommodate wide variations of the main MCU clock frequency (IMB system clock
– F
SYS
), QCLK is generated by a programmable prescaler which divides the MCU sys-
tem clock to a frequency within the specified QCLK tolerance range. To allow the A/D
conversion time to be maximized across the spectrum of system clock frequencies,
the QADC prescaler permits the frequency of QCLK to be software selectable. It also
allows the duty cycle of the QCLK waveform to be programmable.
The software establishes the basic high phase of the QCLK waveform with the PSH
(prescaler clock high time) field in QACR0, and selects the basic low phase of QCLK
with the PSL (prescaler clock low time) field. The duty cycle of the QCLK can be further
modified with the PSA (prescaler add a clock tic) bit in QACR0. The combination of the
PSH and PSL parameters establishes the frequency of the QCLK.
Figure 7-2
shows that the prescaler is essentially a variable pulse width signal gener-
ator. A 5-bit down counter, clocked at the system clock rate, is used to create both the
high phase and the low phase of the QCLK signal. At the beginning of the high phase,
the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that
the high phase is finished, the QCLK is reset. A 3-bit comparator looks for a one’s com-
plement match with the 3-bit PSL value, which is the end of the low phase of the QCLK.
The PSA bit allows the QCLK high-to-low transition to be delayed by a half cycle of the
input clock.
The following sequence summarizes the process of determining what values are to be
put into the prescaler fields in QACR0:
1. Choose the system clock frequency (F
).
2. Choose first-try values for PSH, PSL, and PSA, then skip to step 4.
3. Choose different values for PSH, PSL, and PSA.
4. If High QCLK Time is less than T
(QADC Clock Duty Cycle – Minimum High
Phase Time), return to step 3. Refer to
APPENDIX A ELECTRICAL CHARAC-
TERISTICS
for more information on T
PSH
.
NOTE
High QCLK Time (in ns) = 1000 (PSH + 1 + 0.5 PSA)
÷
F
SYS
(in MHz)
5. If Low QCLK Time is less than T
(QADC Clock Duty Cycle – Minimum Low
Phase Time), return to step 3. Refer to
APPENDIX A ELECTRICAL CHARAC-
TERISTICS
for more information on T
PSL
.
NOTE
Low QCLK Time (in ns) = 1000 (PSL + 1 – 0.5 PSA)
÷
F
SYS
(in MHz)
6. Calculate the QCLK frequency (F
QCLK
).
NOTE
F
QCLK
(in MHz)
= 1000
÷
(High QCLK Time + Low QCLK Time)
7. Choose the number of input sample cycles for a typical input channel.
8. If the calculated conversion times are not sufficient, return to step 3.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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