參數(shù)資料
型號： QADCRM
英文描述： Queued Analog-to-Digital Converter Reference Manual
中文描述： 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊
文件頁數(shù)： 19/122頁
文件大?。?/td> 940K
代理商： QADCRM
QADC
REFERENCE MANUAL
SIGNAL DESCRIPTIONS
MOTOROLA
2-3
the input of a synchronizer during reads and may be used as general-purpose digital
inputs when the applied voltages meet V
IH
and V
IL
requirements. Refer to
APPENDIX
A ELECTRICAL CHARACTERISTICS
for more information on voltage requirements.
Since port B pins are input only, a data direction register is not necessary. The digital
input signal states are read by the software in the lower half of the port data register.
Refer to
APPENDIX B REGISTER SUMMARY
for more information.
2.3 External Trigger Input Pins
The QADC uses two external trigger pins (ETRIG[2:1]). The external trigger inputs are
included in two multifunction port A pins (PQA[4:3]), which are normally used as ana-
log channel input pins. Each of the two input external trigger pins is associated with
one of the scan queues, queue 1 and queue 2. When a queue is in an external trigger
mode, the corresponding external trigger pin is configured as a digital input and the
software programmed input/output direction for the external trigger pins in the data di-
rection register (DDRQA) is ignored. Refer to paragraph 7.7 in
SECTION 7 DIGITAL
CONTROL
for more information.
2.4 Multiplexed Address Output Pins
In the non-multiplexed mode, the 16 channel pins are connected to an internal multi-
plexer which routes the analog signals into the internal A/D converter.
In the externally multiplexed mode, the QADC allows automatic channel selection
through up to four external 8-to-1 selector chips. The QADC provides a 3-bit multi-
plexed address output to the external multiplex chips to allow selection of one of eight
inputs. The multiplexed address output signals (MA[2:0]) can be used as multiplex ad-
dress output bits, or as general I/O.
MA[2:0] are used as the address inputs for up to four 8-channel multiplexer chips (for
example, the MC14051 and the MC74HC4051). Since the MA[2:0] pins are digital out-
puts in the multiplexed mode, the software programmed input/output direction for the
multiplex address pins in the data direction register is ignored.
Refer to paragraph 7.7 in
SECTION 7 DIGITAL CONTROL
for more information on
the use of multiplexed address output pins in the external multiplexed mode.
2.5 Multiplexed Analog Input Pins
In the external multiplexed mode, four of the port B pins are redefined to each repre-
sent eight input channels. Refer to
Table 2-1
.
Refer to paragraph 7.7 in
SECTION 7 DIGITAL CONTROL
for more information.
Table 2-1 Multiplexed Analog Input Channels
Multiplexed Analog Input
ANw
ANx
ANy
ANz
Channels
Even numbered channels from 0 to 14
Odd numbered channels from 1 to 15
Even channels from 16 to 30
Odd channels from 17 to 31
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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