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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊 |
| 文件頁數(shù)： | 22/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
3-2
CONFIGURATION AND CONTROL
QADC
REFERENCE MANUAL
Figure 3-1
shows the three bus cycles which are implemented by the QADC. The fol-
lowing paragraphs describe how the three types of accesses are used, including mis-
aligned and long word accesses.
Figure 3-1 Bus Cycle Accesses
Byte accesses to an even address read or write bits 15 through 8 of a QADC location,
as shown in the top illustration of
Figure 3-1
. In the case of write cycles, bits 7 through
0 of the addressed QADC register are not disturbed. In the case of read cycles, the
QADC provides zeros to the IMB for bits 7 through 0.
Byte accesses to an odd address read or write bits 7 through 0 of a QADC location,
as shown in the center illustration of
Figure 3-1
. In the case of write cycles, bits 15
through 8 of the addressed QADC location are not disturbed. In the case of read cy-
cles, the QADC provides zeros to the IMB for bits 15 through 8.
Word accesses to an even address read or write bits 15 through 0 of a QADC location,
as shown in the lower illustration of
Figure 3-1
. A full 16 bits of data is written to and
read from the QADC location with each access.
QADC BUS CYC ACC
00
INTERMODULE BUS
8-BIT ACCESS OF AN EVEN ADDRESS (ISIZ = 01, A0 = 0)
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[7:0]
QADC LOCATION
W
R
W
R
INTERMODULE BUS
8-BIT ACCESS OF AN ODD ADDRESS (ISIZ = 01, A0 = 1; OR ISIZ = 10, A0 = 1)
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[7:0]
QADC LOCATION
W
R
W
R
INTERMODULE BUS
16-BIT ALIGNED ACCESS (ISIZ = 10, A0 = 0)
DATA[15:8]
DATA[7:0]
DATA[15:8]
DATA[7:0]
QADC LOCATION
W
R
W
R
00
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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