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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊 |
| 文件頁數(shù)： | 74/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
7-28
DIGITAL CONTROL
QADC
REFERENCE MANUAL
To prepare the QADC for a scan sequence, the software writes to the CCW table to
specify the desired channel conversions. The software also establishes the criteria for
initiating the queue execution by programming the queue operating mode. The queue
operating mode determines what type of trigger event causes queue execution to be-
gin. “Trigger event” is used to refer to any of the ways to cause the QADC to begin
executing the CCWs in a queue or subqueue. An “external trigger” is only one of the
possible “trigger events”.
A scan sequence may be initiated by the following:
A software command
Expiration of the periodic/interval timer
External trigger signal
The software also specifies whether the QADC is to perform a single pass through the
queue or is to scan continuously. When a single-scan mode is selected, the software
selects the queue operating mode and sets the single-scan enable bit. When a contin-
uous-scan mode is selected, the queue remains active in the selected queue operat-
ing mode after the QADC completes each queue scan sequence.
During queue execution, the QADC reads each CCW from the active queue and exe-
cutes conversions in four stages:
Initial sample
Transfer
Final sample
Resolution
During initial sample, the selected input channel is connected to the sample capacitor
at the input of the sample buffer amplifier.
During the transfer period, the sample capacitor is disconnected from the multiplexer,
and the stored voltage is buffered and transferred to the RC DAC array.
During the final sample period, the sample capacitor and amplifier are bypassed, and
the multiplexer input charges the RC DAC array directly. Each CCW specifies a final
input sample time of 2, 4, 8, or 16 QCLK cycles. When an analog-to-digital conversion
is complete, the result is written to the corresponding location in the result word table.
The QADC continues to sequentially execute each CCW in the queue until the end of
the queue is detected or a pause bit is found in a CCW.
When the pause bit is set in the current CCW, the QADC stops execution of the queue
until a new trigger event occurs. The pause status flag bit is set, which may cause an
interrupt to notify the software that the queue has reached the pause state. After the
trigger event occurs, the paused state ends and the QADC continues to execute each
CCW in the queue until another pause is encountered or the end of the queue is de-
tected.
The following indicate the end-of-queue condition:
The CCW channel field is programmed with 63 ($3F) to specify the end of the
queue.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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