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參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁數(shù)： | 85/122頁 |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
INTERRUPTS
MOTOROLA
8-5
Figure 8-2 QADC Interrupt Vector Format
After reset, and before the IVB field is initialized by the software, the IVB field has a
default value of $0F, which corresponds to the uninitialized interrupt exception vector.
8.8 Initializing the QADC for Interrupt Driven Operation
The following steps are required to ensure proper operation of QADC interrupt pro-
cesses.
1. Set the three-bit interrupt priority mask. This mask is located in the CPU32 sta-
tus register or the CPU16 condition code register.
2. Assign the QADC a unique non-zero IARB value. The IARB field is located in
the QADCMCR. The lowest priority IARB value is %0001, and the highest pri-
ority IARB value is %1111.
3. Set the interrupt request levels for queue 1 and queue 2 in the IRL1 and IRL2
bit fields, located in the QADCINT. They should be higher than the interrupt
mask value in order for the interrupt requests to be recognized. Level 001 is the
lowest priority interrupt request, and level 111 is the highest priority request.
4. Establish the six high-order bits of the eight-bit IVB field in the QADCINT. The
QADC provides the two low-order vector bits to identify one of four QADC inter-
rupt requests.
5. Load each interrupt service routine. The IVB number for each QADC interrupt
request corresponds to a specific vector in the exception vector table. Refer to
the CPU16 Reference Manual(CPU16RM/AD) or the CPU32 Reference Man-
ual (CPU32RM/AD) for information on locating an entry in the exception vector
table given a vector number. Each vector in the exception vector table points to
the beginning address of an exception handler routine.
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IVB0
IVB1
IVB3
IVB4
IVB5
IVB6
IVB2
IVB7
1
1
0
1
1
0
0
0
— QUEUE 1 COMPLETION SOFTWARE INTERRUPT
— QUEUE 1 PAUSE SOFTWARE INTERRUPT
— QUEUE 2 COMPLETION SOFTWARE INTERRUPT
— QUEUE 2 PAUSE SOFTWARE INTERRUPT
VECTOR BITS PROVIDED
BY QADC
INTERRUPT REGISTER PROVIDED
BY SOFTWARE
TO CPU DURING SOFTWARE
INTERRUPT ARBITRATION
(FROM QADC MODULE)
QADC SWI VECT
IVB0
IVB1
IVB3
IVB4
IVB5
IVB6
IVB2
IVB7
SOFTWARE INTERRUPT VECTOR PROVIDED
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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