參數(shù)資料
型號(hào)： QADCRM
英文描述： Queued Analog-to-Digital Converter Reference Manual
中文描述： 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè)
文件頁數(shù)： 78/122頁
文件大小： 940K
代理商： QADCRM
MOTOROLA
7-32
DIGITAL CONTROL
QADC
REFERENCE MANUAL
If the CCW channel field specifies a reserved channel number (channels 32 to 47) or
an invalid channel number (channels 4 to 31 in the non-multiplexed mode), the low ref-
erence level (V
RL
) is converted. The channel field is programmed for channel 63 to in-
dicate the end of the queue. Channels 60 to 63 are special internal channels. When
one of the special channels is selected, the sampling amplifier is not used. The value
of V
RL
, V
RH
, or V
DDA
/2 is placed directly onto the converter. Also for the internal spe-
cial channels, programming any input sample time other than two has no benefit ex-
cept to lengthen the overall conversion time.
7.8 Result Word Table
The result word table is a RAM, 40 words long and 10 bits wide. An entry is written by
the QADC after completing an analog conversion specified by the corresponding CCW
table entry. Software can read or write the result word table, but in normal operation,
the software reads the result word table to obtain analog conversions from the QADC.
Unimplemented bits are read as zeros, and write operations do not have any effect.
While there is only one result word table, the data can be accessed in three different
data formats:
Right justified in the 16-bit word, with zeros in the higher order unused bits.
Left justified, with the most significant bit inverted to form a sign bit, and zeros in
the unused lower order bits.
Left justified, with zeros in the lower order unused bits.
Table 7-9 Multiplexed Channel Assignments and Pin Designations
Multiplexed Input Pins
Channel Number in CCW CHAN
Field
Binary
Port Pin
Name
PQB0
PQB1
PQB2
PQB3
—
PQB4
PQB5
PQB6
PQB7
PQA0
PQA1
PQA2
PQA3
PQA4
PQA5
PQA6
PQA7
V
RL
V
RH
—
—
Analog
Pin Name
ANw
ANx
ANy
ANz
—
AN48
AN49
AN50
AN51
—
—
—
AN55
AN56
AN57
AN58
AN59
Low Ref
High Ref
—
Other
Functions
—
—
—
—
Reserved
—
—
—
—
MA0
MA1
MA2
ETRIG1
ETRIG2
—
—
—
—
—
V
DDA
/2
End of Queue Code
Pin Type
Decimal
Input
Input
Input
Input
—
Input
Input
Input
Input
00xxx0
00xxx1
01xxx0
01xxx1
10xxxx
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
0 to 14 even
1 to 15 odd
16 to 30 even
17 to 31 odd
32 to 47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
—
—
—
111111
63
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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