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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 25/122頁(yè) |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
CONFIGURATION AND CONTROL
MOTOROLA
3-5
NOTE
Some CPUs do not support supervisor/user space selection, and are
always in the supervisor access mode. In such cases, the SUPV bit
has no meaning or effect.
The supervisor-only data space segment contains the QADC global registers, which
include the QADCMCR, the QADCTEST, and the QADCINT. The supervisor/unre-
stricted space designation for the CCW table, the result word table, and the remaining
QADC registers are programmable.
3.3.4 Interrupt Arbitration Priority
Each module that can generate interrupts, including the QADC, has an IARB (interrupt
arbitration number) field in the QADCMCR. Each IARB field must have a different val-
ue. During an interrupt acknowledge cycle, IARB permits arbitration among simulta-
neous interrupts of the same priority level.
The reset value of IARB in the QADCMCR is $F. This prevents QADC interrupts from
being discarded. Initialization software must set the IARB field to a lower value in the
range $F (highest priority) to $1 (lowest priority) if lower priority interrupts are to be ar-
bitrated.
Refer to
SECTION 8 INTERRUPTS
for more information.
3.3.5 QADC Module Configuration Register
The QADCMCR contains fields and bits that control freeze and stop modes and deter-
mines the privilege level required to access most registers. It also contains the IARB
field.
STOP — Stop Enable
0 = Disable stop mode.
1 = Enable stop mode.
FRZ — Freeze Enable
0 = Ignores the IMB internal FREEZE signal.
1 = Finish any current conversion, then freeze
SUPV — Supervisor/Unrestricted Data Space
0 = Only the module configuration register, test register, and interrupt register are
designated as supervisor-only data space. Access to all other locations is un-
restricted.
1 = All QADC registers and tables are designated as supervisor-only data space.
QADCMCR —
Module Configuration Register
$####00
15
14
FRZ
13
12
11
NOT USED
10
9
8
7
6
5
4
3
2
1
0
STOP
RESET:
0
SUPV
NOT USED
IARB
0
1
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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