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參數(shù)資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊 |
| 文件頁數(shù)： | 62/122頁 |
| 文件大?。?/td> | 940K |
| 代理商： | QADCRM |
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MOTOROLA
7-16
DIGITAL CONTROL
QADC
REFERENCE MANUAL
PSL[2:0] — Prescaler Clock Low Time
The PSL field selects the QCLK low time in the prescaler. Refer to
APPENDIX A
ELECTRICAL CHARACTERISTICS
for information on F
values. To keep the
QCLK within the specified range, the PSL field selects the low time of the QCLK, which
can range from one to eight system clock cycles. The minimum low time for the clock
is specified as T
PSL
.
Table 7-2
displays the bits in PSL field which enable a range of QCLK low times.
7.6.2 Control Register 1
Control register 1 is the mode control register for the operation of queue 1. The appli-
cations software defines the queue operating mode for the queue, and may enable a
completion and/or pause interrupt. All of the control register fields are read/write data.
However, the SSE1 bit always reads as zero unless the test mode is enabled. Most of
the bits are typically written once when the software initializes the QADC, and not
changed afterwards.
CIE1 — Queue 1 Completion Interrupt Enable
CIE1 enables an interrupt upon completion of queue 1. The interrupt request is initiat-
ed when the conversion is complete for the CCW in queue 1.
0 = Disable the queue completion interrupt associated with queue 1.
1 = Enable an interrupt after the conversion of the sample requested by the last
CCW in queue 1.
PIE1 — Queue 1 Pause Interrupt Enable
PIE1 enables an interrupt when queue 1 enters the pause state. The interrupt request
is initiated when conversion is complete for a CCW that has the pause bit set.
0 = Disable the pause interrupt associated with queue 1.
1 = Enable an interrupt after the conversion of the sample requested by a CCW in
queue 1 which has the pause bit set.
Table 7-3 Prescaler Clock Low Times
PSL[2:0]
000
001
010
011
100
101
110
111
QCLK Low Time
1 System Clock Cycle
2 System Clock Cycles
3 System Clock Cycles
4 System Clock Cycles
5 System Clock Cycles
6 System Clock Cycles
7 System Clock Cycles
8 System Clock Cycles
QACR1 —
Control Register 1
$####0C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIE1
PIE1
SSE1
NOT USED
MQ1
NOT USED
RESET:
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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