參數(shù)資料
型號(hào)： QADCRM
英文描述： Queued Analog-to-Digital Converter Reference Manual
中文描述： 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè)
文件頁(yè)數(shù)： 15/122頁(yè)
文件大小： 940K
代理商： QADCRM
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QADC
REFERENCE MANUAL
OVERVIEW
MOTOROLA
1-3
Access to supervisor-only data space is permitted only when the software is operating
in supervisor access mode. Assignable data space can be either restricted to supervi-
sor-only access or unrestricted to both supervisor and user data space addresses.
The SUPV bit in the module configuration register designates the assignable space as
supervisor or unrestricted.
Attempts to read a supervisor-only data space when not in the supervisor access
mode causes a value of $0000 to be returned. Attempts to read assignable data space
in the unrestricted access mode when the space is programmed as supervisor space
causes a value of $FFFF to be returned. Attempts to write supervisor-only or supervi-
sor-assigned data space when in the unrestricted access mode has no effect.
The CPU32 indicates the supervisor and user space access with the function code sig-
nal FC2 on the IMB bus. CPU16 does not support supervisor/user space selection,
and is always in the supervisor access mode. In such cases, the SUPV bit has no
meaning or effect.
The first block of the address map contains the nine words used for control, status,
port, and test information. The control registers permit the software to initialize the
QADC for the desired configuration and queue operating mode. Also included are the
status bits that the software may read to identify an interrupt source and to determine
NOTES:
1. S = Supervisor only
2. S/U = Unrestricted or supervisor depending on the state of the SUPV bit in the QADCMCR.
Table 1-1 QADC Address Map
Access
S
S
S
S/U
S/U
S/U
S/U
S/U
S/U
—
Address
$####00
$####02
$####04
$####06
$####08
$####0A
$####0C
$####0E
$####10
$####12–
$####2E
$####30–
$####7E
$####80–
$####AE
$####B0–
$####FE
$####00–
$####2E
$####30–
$####7E
$####80–
$####AE
$####B0–
$####FE
Offset
$000
$002
$004
$006
$008
$00A
$00C
$00E
$010
$012–
$02E
$030–
$07E
$080–
$0AE
$0B0–
$0FE
$100–
$12E
$130–
$17E
$180–
$1AE
$1B0–
$1FE
15
8
7
0
1
MODULE CONFIGURATION REGISTER (QADCMCR)
TEST REGISTER (QADCTEST)
INTERRUPT REGISTER (QADCINT)
PORT A DATA (PORTQA)
PORT DATA DIRECTION REGISTER (DDRQA)
CONTROL REGISTER 0 (QACR0)
CONTROL REGISTER 1 (QACR1)
CONTROL REGISTER 2 (QACR2)
STATUS REGISTER (QASR)
RESERVED
2
PORT B DATA (PORTQB)
S/U
CONVERSION COMMAND WORD (CCW) TABLE
—
RESERVED
S/U
RESULT WORD TABLE
RIGHT JUSTIFIED, UNSIGNED RESULT REGISTER (RJURR)
RESERVED
—
S/U
RESULT WORD TABLE
LEFT JUSTIFIED, SIGNED RESULT REGISTER (LJSRR)
RESERVED
—
S/U
RESULT WORD TABLE
LEFT JUSTIFIED, UNSIGNED RESULT REGISTER (LJURR)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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